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AD7626

Rev. A | Page 17 of

TYPICAL CONNECTION DIAGRAM

AD7626

CREF

10µF1, 2

V+

ADR4348

ADR444

CONVERSION4

CONTROL

CMOS (CNV+ ONLY)

LVDS CNV+ AND CNV–

USING 100

Ω

TERMINATION RESISTOR

DIGITAL INTERFACE SIGNALS

DIGITAL HOST

LVDS TRANSMIT AND RECEIVE

VDD1

VDD2

CAP1

REFIN

EN0

EN1

VDD2

GND

IN+

IN–

VCM

VDD1

VDD2

10nF

100nF

10µF

ADR2808

VIO

10k

Ω3

10k

Ω

CONTROL FOR

ENABLE

PINS

VIO

(2.5V)

100

Ω

100

Ω

PADDLE

CAPACITOR ON OUTPUT

FOR STABILITY

10µF1

100nF

FERRITE

BEAD6

VDD1

(5V)

VDD2

(2.5V)

VDD1

(5V)

VDD2

(2.5V)

100nF

VDD2

(2.5V)

IN+

IN–

VCM

SEE THE DRIVING

THE AD7625 SECTION7

100

Ω

100

Ω

1 SEE THE LAYOUT, DECOUPLING, AND GROUNDING SECTION.

2 C

REF IS USUALLY A 10µF CERAMIC CAPACITOR WITH LOW ESR AND ESL.

3 USE PULL-UP OR PULL-DOWN RESISTORS TO CONTROL EN0 AND EN1 DURING POWER-UP. EN0 AND EN1 INPUTS CAN BE

FIXED IN HARDWARE OR CONTROLLED USING A DIGITAL HOST (EN0 = 0 AND EN1 = 0 PUTS THE ADC IN POWER-DOWN).

4 OPTION TO USE A CMOS (CNV+) OR LVDS (CNV±) INPUT TO CONTROL CONVERSIONS.

5 TO ENABLE SELF-CLOCKED MODE, TIE DCO+ TO GND.

6 CONNECT PIN 19 AND PIN 20 TO VDD1 SUPPLY; ISOLATE THE TRACE TO PIN 19 AND PIN 20 FROM THE TRACE TO PIN 1 USING A

FERRITE BEAD SIMILAR TO WURTH 74279266.

7 SEE THE DRIVING THE AD7626 SECTION FOR DETAILS ON AMPLIFIER CONFIGURATIONS.

8 SEE THE VOLTAGE REFERENCE OPTIONS SECTION FOR DETAILS.

Figure 31. Typical Application Diagram

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