CBTL06121 datasheet(7/19 Pages) NXP

7 / 19 page

CBTL06121_1

Product data sheet

Rev. 01 — 23 May 2008

7 of 19

NXP Semiconductors

CBTL06121

Gen1 hex display multiplexer

6.2 Pin description

Table 2.

Pin description

Symbol

Type

Description

Pinout A Pinout B

SEL

3.3 V low-voltage CMOS

single-ended input

SEL controls the MUX through a ﬂow-through latch.

LE_N

3.3 V low-voltage CMOS

single-ended input

The latch gate is controlled by LE_N.

XSD

3.3 V low-voltage CMOS

single-ended input

Optional shutdown pin. Should be driven HIGH or

connected to VDD for normal operation. When LOW, all

paths are switched off (non-conducting) and supply current

consumption is minimized.

RX0+

differential input

Differential input from PCIe connector or device. RX0+

makes a differential pair with RX0

−. RX0+ is passed

through to the OUT+ pin when SEL = 0.

RX0

−

differential input

Differential input from PCIe connector or device. RX0

−

makes a differential pair with RX0+. RX0

− is passed

through to the OUT

− pin when SEL = 0.

RX1+

differential input

Differential input from PCIe connector or device. RX1+

makes a differential pair with RX1

−. RX1+ is passed

through to the X+ pin when SEL = 0.

RX1

−

differential input

Differential input from PCIe connector or device. RX1

−

makes a differential pair with RX1+. RX1

− is passed

through to the X

− pin on a path that matches the RX1+ to

X+ path.

IN_0+

differential input