LPC2194 datasheet(17/40 Pages) NXP

17 / 40 page

LPC2194_5

Product data sheet

Rev. 05 — 10 December 2007

17 of 40

NXP Semiconductors

LPC2194

Single-chip 16/32-bit microcontroller

6.14.1 Features

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

• Timer or external event counter operation

• Four 32-bit capture channels per timer that can take a snapshot of the timer value

when an input signal transitions. A capture event may also optionally generate an

interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Four external outputs per timer corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

6.14.2 Features available in LPC2194/01 only

The LPC2194/01 can count external events on one of the capture inputs if the external

pulse lasts at least one half of the period of the PCLK. In this conﬁguration, unused

capture lines can be selected as regular timer capture inputs, or used as external

interrupts.

• Timer can count cycles of either the peripheral clock (PCLK) or an externally supplied

clock.

• When counting cycles of an externally supplied clock, only one of the timer’s capture

inputs can be selected as the timer’s clock. The rate of such a clock is limited to

PCLK / 4. Duration of HIGH/LOW levels on the selected CAP input cannot be shorter

than 1 / (2PCLK).

6.15 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined

amount of time.

6.15.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect/incomplete feed sequence causes reset/interrupt if enabled.

LPC2194 Datasheet(PDF) 17 Page - NXP Semiconductors

LPC2194 Datasheet(HTML) 17 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL