LPC2194 datasheet(16/40 Pages) NXP

16 / 40 page

LPC2194_5

Product data sheet

Rev. 05 — 10 December 2007

16 of 40

NXP Semiconductors

LPC2194

Single-chip 16/32-bit microcontroller

6.12 SPI serial I/O controller

The LPC2194 each contain two SPIs. The SPI is a full duplex serial interface, designed to

be able to handle multiple masters and slaves connected to a given bus. Only a single

master and a single slave can communicate on the interface during a given data transfer.

During a data transfer the master always sends a byte of data to the slave, and the slave

always sends a byte of data to the master.

6.12.1 Features

• Compliant with Serial Peripheral Interface (SPI) speciﬁcation.

• Synchronous, Serial, Full Duplex communication.

• Combined SPI master and slave.

• Maximum data bit rate of 1

⁄

8 of the input clock rate.

6.12.2 Features available in LPC2194/01 only

• Eight to 16 bits per frame.

• When the SPI interface is used in Master mode, the SSELn pin is not needed (can be

used for a different function).

6.13 SSP controller (LPC2194/01 only)

The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. Only a single master and a single

slave can communicate on the bus during a given data transfer. Data transfers are in

principle full duplex, with frames of four to 16 bits of data ﬂowing from the master to the

slave and from the slave to the master.

While the SSP and SPI1 peripherals share the same physical pins, it is not possible to

have both of these two peripherals active at the same time. The application can switch on

the ﬂy from SPI1 to SSP and back.

6.13.1 Features

• Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National

Semiconductor’s Microwire buses.

• Synchronous serial communication.

• Master or slave operation.

• 8-frame FIFOs for both transmit and receive.

• Four to 16 bits per frame.

6.14 General purpose timers

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an

externally supplied clock and optionally generate interrupts or perform other actions at

speciﬁed timer values, based on four match registers. It also includes four capture inputs

to trap the timer value when an input signal transitions, optionally generating an interrupt.

Multiple pins can be selected to perform a single capture or match function, providing an

application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

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