TMS320DM6441 datasheet(32/232 Pages) TI

32 / 232 page

TMS320DM6441

Digital Media System-on-Chip

SPRS359D – SEPTEMBER 2006 – REVISED MARCH 2008

www.ti.com

Table 3-9. EMIFA Terminal Functions (continued)

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

NAME

NO.

EMIFA FUNCTIONAL PINS: NAND / SMARTMEDIA / xD

EM_A[1]/

This pin is multiplexed between EMIFA and HPI.

(ALE)/

I/O/Z

DVDD18

For NAND/SmartMedia/xD, it is Address Latch Enable output (ALE).

HHWIL

EM_A[2]/

This pin is multiplexed between EMIFA and HPI.

(CLE)/

I/O/Z

DVDD18

For NAND/SmartMedia/xD, this pin is the Command Latch Enable output (CLE).

HCNTL0

EM_WAIT/

(RDY/BSY)/

IPU

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.

I/O/Z

IORDY/

DVDD18

For NAND/SmartMedia/xD, it is ready/busy input (RDY/BSY).

HRDY

EM_OE/

(RE)/

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.

(IORD)/

I/O/Z

DVDD18

For NAND/SmartMedia/xD, it is read enable output (RE).

DIOR/

HDS1

EM_WE

(WE)

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.

(IOWR)/

I/O/Z

DVDD18

For NAND/SmartMedia/xD, it is write enable output (WE).

DIOW/

HDS2

This pin is multiplexed between EMIFA and HPI.

EM_CS2/

For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous

I/O/Z

DVDD18

HCS

memories (i.e. NOR flash) or NAND flash. This is the chip select for the default boot

and ROM boot modes.

For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with asynchronous

EM_CS3

I/O/Z

DVDD18

memories (i.e. NOR flash) or NAND flash.

EM_CS4/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip

GPIO9/

I/O/Z

DVDD18

Select 4 output EM_CS4 for use with asynchronous memories (i.e., NOR flash) or

VLYNQ_SCRUN

NAND flash.

EM_CS5/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip

GPIO8/

I/O/Z

DVDD18

Select 5 output EM_CS5 for use with asynchronous memories (i.e., NOR flash) or

VLYNQ_CLOCK

NAND flash.

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