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TMS320DM6441 Datasheet(PDF) 61 Page - Texas Instruments

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Part # TMS320DM6441
Description  Digital Media System-on-Chip
PDF  232 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320DM6441 Datasheet(HTML) 61 Page - Texas Instruments

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4.2.2
Power Configurations after Reset
4.3 Bootmode
TMS320DM6441
Digital Media System-on-Chip
www.ti.com
SPRS359D – SEPTEMBER 2006 – REVISED MARCH 2008
Setting the DSPPWRON bit to a value of 1 closes (enables) the switch and enables the DSP power
domain. The default switch value is determined by the DSP_BT configuration input. If DSP self boot is
selected (DSP_BT=1), the DSP will be powered-up and DSPPWRON will be set to a value of 1. For ARM
boot operation (DSP_BT=0), DSPPWRON will be set to the disable value of 0 and must be set by the
ARM before the DSP domain power is turned on.
Figure 4-1. CHP_SHRTSW Register
31
1
0
RESERVED
DSPPWRON
R-0000 0000 0000 0000 0000 0000 0000 000
R/W-L
LEGEND: R = Read, W = Write, n = value at reset, L = pin state latched at reset rising
Table 4-2. CHP_SHRTSW Register Field Descriptions
Bit
Field
Value
Description
31 - 1
RESERVED
Reserved
0
DSPPWRON
DSP power domain enable
0
Shorting switch open
1
Shorting switch closed
The VDD3P3V_PWDN register controls power to the 3.3V I/O buffers for MMC/SD/SDIO, Memory
Stick/Memory Stick PRO, and GPIOV33. The 3.3V I/Os are separated into two groups for independent
control as shown in Figure 4-2 and described in Table 4-3. By default, these pins are all disabled at reset.
Figure 4-2. VDD3P3V_PWDN Register
31
2
1
0
RESERVED
IOPWDN1
IOPWDN0
R-0000 0000 0000 0000 0000 0000 0000 00
R/W-1
R/W-1
LEGEND: R = Read, W = Write, n = value at reset
Table 4-3. VDD3P3V_PWDN Register Field Descriptions
Bit
Field
Value
Description
31 - 2
RESERVED
Reserved
1
IOPWDN1
Memory Stick/Memory Stick PRO, MMC/SD/SDIO powerdown controls.
0
I/O buffers powered up
1
I/O buffers powered down
0
IOPWDN0
GIOV33 I/O powerdown controls GIOV33[16:0] pins.
0
I/O buffers powered up
1
I/O buffers powered down
The device is booted through multiple means: pin states captured at reset, primary bootloaders within
internal ROM or EMIFA, and secondary user bootloaders from peripherals or external memories. Boot
modes, pin configurations, and register configurations required for booting the device, are described in the
following sections.
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Device Configurations
61



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