TMS320DM6441 datasheet(14/232 Pages) TI

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3.3.11 Power and Sleep Controller (PSC)

3.3.12 ARM Interrupt Controller (AINTC)

3.3.13 System Module

3.3.14 Power Management

3.4 DSP Subsystem

3.4.1

C64x+ DSP CPU Description

TMS320DM6441

Digital Media System-on-Chip

SPRS359D – SEPTEMBER 2006 – REVISED MARCH 2008

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The PLLs are briefly described in this document in Section 7.6, Clock PLLs. For more detailed information

on the PLLs and PLL Controller register descriptions, see Section 3.8.3, Documentation Support, of this

document for the TMS320DM644x ARM Subsystem Reference Guide (literature number SPRUE14).

The ARM subsystem includes the power and sleep controller (PSC). Through register settings accessible

by the ARM9, the PSC provides two levels of power savings: peripheral/module clock gating and power

domain shut-off. Brief details on the PSC are given in Section 7.3, Power Supplies. For more detailed

information and complete register descriptions for the PSC, see Section 3.8.3, Documentation Support, for

the TMS320DM644x ARM Subsystem Reference Guide (literature number SPRUE14).

The ARM interrupt controller (AINTC) accepts device interrupts and maps them to either the ARM’s IRQ

(interrupt request) or FIQ (fast interrupt request). The ARM interrupt controller is briefly described in this

document in the Interrupts section. For detailed information on the ARM interrupt controller, see

Section 3.8.3, Documentation Support, for the ARM subsystem guide.

The ARM subsystem includes the system module. The system module consists of a set of registers for

configuring and controlling a variety of system functions. For details and register descriptions for the

system module, see Section 4, Device Configurations, and see Section 3.8.3, Documentation Support, for

the TMS320DM644x ARM Subsystem Reference Guide (literature number SPRUE14).

DM6441 has several means of managing power consumption. There is extensive use of clock gating,

which reduces the power used by global device clocks and individual peripheral clocks. Clock

management can be utilized to reduce clock frequencies in order to reduce switching power. For more

details on power management techniques, see Section 4, Device Configurations, Section 7, Peripheral

and Electrical Specifications, and see Section 3.8.3, Documentation Support, for the TMS320DM644x

ARM Subsystem Reference Guide (literature number SPRUE14).

The DSP subsystem includes the following features:

• C64x+ DSP CPU

• 32KB L1 program (L1P)/cache (up to 32KB)

• 80KB L1 data (L1D)/cache (up to 32KB)

• 64KB unified mapped RAM/cache (L2)

• Little endian

The C64x+ central processing unit (CPU) consists of eight functional units, two register files, and two data

paths as shown in Figure 3-1. The two general-purpose register files (A and B) each contain 32 32-bit

registers for a total of 64 registers. The general-purpose registers can be used for data or can be data

address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data,

40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored

in register pairs, with the 32 LSBs of data placed in an even register and the remaining eight or 32 MSBs

in the next upper register (which is always an odd-numbered register).

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one

instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units

perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from

memory to the register file and store results from the register file into memory.

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