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P89LPC9103 Datasheet(PDF) 52 Page - NXP Semiconductors |
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P89LPC9103 Datasheet(HTML) 52 Page - NXP Semiconductors |
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52 / 61 page ![]() P89LPC9102_9103_9107_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 10 July 2007 52 of 61 NXP Semiconductors P89LPC9102/9103/9107 8-bit microcontrollers with two-clock accelerated 80C51 core 12.1 Waveforms Fig 19. Shift register mode timing (P89LPC9103/9107) 01 2 3 4 5 6 7 valid valid valid valid valid valid valid valid TXLXL 002aaa906 set TI set RI tXHQX tQVXH tXHDV tXHDX clock output data write to SBUF input data clear RI Fig 20. External clock timing tCHCL tCLCX tCHCX Tcy(clk) tCLCH 002aaa907 0.2VDD + 0.9 V 0.2VDD − 0.1 V VDD − 0.5 V 0.45 V |
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