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P89LPC985FDH Datasheet(PDF) 73 Page - NXP Semiconductors |
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P89LPC985FDH Datasheet(HTML) 73 Page - NXP Semiconductors |
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73 / 85 page  P89LPC980_982_983_985_2 © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 02 — 8 February 2010 73 of 85 NXP Semiconductors P89LPC980/982/983/985 8-bit microcontroller with accelerated two-clock 80C51 core 11.1 Waveforms Fig 22. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) tCHCL tCLCX tCHCX Tcy(clk) tCLCH 002aaa907 Fig 23. Shift register mode timing 0 1 23 45 6 7 valid valid valid valid valid valid valid valid TXLXL 002aaa906 set TI set RI tXHQX tQVXH tXHDV tXHDX clock output data write to SBUF input data clear RI Fig 24. SPI master timing (CPHA = 0) TSPICYC tSPICLKH tSPICLKH tSPICLKL tSPICLKL master LSB/MSB out master MSB/LSB out tSPIDH tSPIDSU tSPIF tSPIOH tSPIDV tSPIR tSPIDV tSPIF tSPIR tSPIF tSPIR SS SPICLK (CPOL = 0) (output) 002aaa908 SPICLK (CPOL = 1) (output) MISO (input) MOSI (output) LSB/MSB in MSB/LSB in |
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