MC9S08JS16CFK datasheet(19/32 Pages) FREESCALE

19 / 32 page

Electrical Characteristics

MC9S08JS16 Series MCU Data Sheet, Rev. 4

Freescale Semiconductor

3.9

AC Characteristics

This section describes AC timing characteristics for each peripheral system.

3.9.1

Control Timing

3 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

BUS.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for

a given interval.

4 Jitter measurements are based upon a 48 MHz clock frequency.

5 625 ns represents 5 time quanta for CAN applications, under worst case conditions of 8 MHz CAN bus clock, 1 Mbps CAN

bus speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge

and the sample point of a bit using 8 time quanta per bit.

6 Below D

lock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG

is already in lock, then the MCG may stay in lock.

7 Below D

unl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.

Figure 13. Control Timing

Num

Parameter

Symbol

Min

Typical1

1 Typical values are based on characterization data at V

DD = 5.0 V, 25 °C unless otherwise stated.

Max

Unit

Bus frequency (tcyc = 1/fBus)fBus

—

MHz

Internal low-power oscillator period

tLPO

700

—

1300

μs

External reset pulse width2

(tcyc = 1/fSelf_reset)

2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to

override reset requests from internal sources.

textrst

1.5

× t

Self_reset

——

Reset low drive

trstdrv

× t

cyc

——

Active background debug mode latch setup

time

tMSSU

—

Active background debug mode latch hold

time

tMSH

—

IRQ pulse width

Asynchronous path2

Synchronous path3

3 This is the minimum pulse width guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not

be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.

tILIH, tIHIL

100

1.5

× t

cyc

——

KBIPx pulse width

Asynchronous path2

Synchronous path3

tILIH, tIHIL

100

1.5

× t

cyc

——

Port rise and fall time (load = 50 pF)4

Slew rate control disabled (PTxSE = 0)

Slew rate control enabled (PTxSE = 1)

4 Timing is shown with respect to 20% V

DD and 80% VDD levels. Temperature range –40°C to 85°C.

tRise, tFall

—

MC9S08JS16CFK Datasheet(PDF) 19 Page - Freescale Semiconductor, Inc

MC9S08JS16CFK Datasheet(HTML) 19 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL