PCA2125 datasheet(5/36 Pages) NXP

5 / 36 page

PCA2125_1

Product data sheet

Rev. 01 — 28 July 2008

5 of 36

NXP Semiconductors

PCA2125

SPI Real-time clock/calendar

[2]

Ten’s place in 24 h mode.

8.2 Reset

The PCA2125 includes an internal reset circuit which is active whenever the oscillator is

stopped; see Figure 3. The oscillator can be stopped, for example, by connecting one of

the oscillator pins OSCI or OSCO to ground.

The oscillator is considered to be stopped during the time between power-up and stable

crystal resonance; see Figure 4. This time can be in the range 200 ms to 2 s depending

on crystal type, temperature and supply voltage. Whenever an internal reset occurs, the

reset ﬂag bit RF is set.

Fig 3.

Reset system

Fig 4.

Power-on reset

Table 5.

Bits labeled ‘-’ are not implemented and will return a ‘0’ when read. Bits labeled ‘X’ are undeﬁned at

power-up and unchanged by subsequent resets.

Address

Bit

00h

Control_1

01h

Control_2

00000000

02h

Seconds

XXXXXXX

03h

Minutes

XXXXXXX

04h

Hours

XXXXXX

05h

Days

XXXXXX

06h

Weekdays

-----

001aaf898

SDI

0 = override inactive

0 = clear override mode

0 = stopped, 1 = running

osc stopped

1 = override active

1 = override possible

CLEAR

POR

OVERRIDE

Bit

POR_OVRD

OSCILLATOR

reset

001aaf897

chip in reset

chip not in reset

VDD

oscillation

internal

reset

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