PCA8565TS datasheet(7/39 Pages) NXP

7 / 39 page

PCA8565_2

Product data sheet

Rev. 02 — 16 June 2009

7 of 39

NXP Semiconductors

PCA8565

Real time clock/calendar

9.2 Control registers

9.2.1 Register Control_1

[1]

Default value.

[2]

Bits labeled as N should always be written with logic 0.

9.2.2 Register Control_2

[1]

Bits labeled as N should always be written with logic 0.

[2]

Default value.

Table 5.

Bit

Symbol

Value

Description

TEST1

0[1]

normal mode

EXT_CLK test mode

0[2]

default value

5STOP

0[1]

RTC source clock runs

all RTC divider chain ﬂip-ﬂops are asynchronously set to

logic 0;

the RTC clock is stopped (CLKOUT at 32.768 kHz is still

available)

0[2]

default value

TESTC

power-on reset override facility is disabled;

set to logic 0 for normal operation

1[1]

power-on reset override may be enabled

2 to 0 N

000[2]

default value

Table 6.

Bit

Symbol

Value

Description

7 to 5 N

000[1]

default value

TI_TP

0[2]

INT is active when TF is active (subject to the status of

TIE)

INT pulses active according to Table 26 (subject to the

status of TIE);

Remark: note that if AF and AIE are active then INT will

be permanently active

3AF

0[2]

alarm ﬂag inactive

alarm ﬂag active

2TF

0[2]

timer ﬂag inactive

timer ﬂag active

AIE

0[2]

alarm interrupt disabled

alarm interrupt enabled

TIE

0[2]

timer interrupt disabled

timer interrupt enabled

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