PCA9517_3

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 — 30 January 2007

5 of 19

NXP Semiconductors

PCA9517

7.

Application design-in information

A typical application is shown in Figure 4. In this example, the system master is running

Master devices can be placed on either bus.

The PCA9517 is 5 V tolerant, so it does not require any additional circuitry to translate

between 0.9 V to 5.5 V bus voltages and 2.7 V to 5.5 V bus voltages.

B-side to turn on, causing the B-side to pull down to about 0.5 V. When the B-side of the

PCA9517 falls, first a CMOS hysteresis type input detects the falling edge and causes the

internal driver on the A-side to turn on and pull the A-side pin down to ground. In order to

illustrate what would be seen in a typical application, refer to Figure 8 and Figure 9. If the

bus master in Figure 4 were to write to the slave through the PCA9517, waveforms shown

except that the HIGH level may be as low as 0.9 V, and the turn on and turn off of the

acknowledge signals are slightly delayed.

On the B bus side of the PCA9517, the clock and data lines would have a positive offset

the end of the acknowledge, the level rises only to the LOW level set by the driver in the

HIGH. It is important to note that any arbitration or clock stretching events require that the

recognized by the PCA9517 and then transmitted to the A bus side.

Multiple PCA9517 A-sides can be connected in a star configuration (Figure 5), allowing all

nodes to communicate with each other.

Multiple PCA9517s can be connected in series (Figure 6) as long as the A-side is

segments. The number of devices that can be connected in series is limited by repeater

delay/time-of-flight considerations on the maximum bus speed requirements.

Fig 4.

Typical application

002aac201

PCA9517

SDAB

SDAA

SCLB

SCLA

EN

10 k

Ω

10 k

Ω

SDA

SCL

BUS

MASTER

400 kHz

SLAVE

400 kHz

SDA

SCL

bus B

bus A

1.2 V

3.3 V

10 k

Ω

10 k

Ω