PCA9534_3

© NXP B.V. 2006. All rights reserved.

Product data sheet

Rev. 03 — 6 November 2006

5 of 25

NXP Semiconductors

PCA9534

6.1.3 Register 1 - Output Port register

This register reflects the outgoing logic levels of the pins defined as outputs by Register 3.

Bit values in this register have no effect on pins defined as inputs. Reads from this register

return the value that is in the flip-flop controlling the output selection, not the actual pin

value.

6.1.4 Register 2 - Polarity Inversion register

This register allows the user to invert the polarity of the Input Port register data. If a bit in

this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in

this register is cleared (written with a ‘0’), the Input Port data polarity is retained.

Table 4.

Register 0 - Input Port register bit description

Bit

Symbol

Access

Value

Description

7

I7

read only

X

determined by externally applied logic level

6

I6

read only

X

5

I5

read only

X

4

I4

read only

X

3

I3

read only

X

2

I2

read only

X

1

I1

read only

X

0

I0

read only

X

Table 5.

Register 1 - Output Port register bit description

Legend: * default value.

Bit

Symbol

Access

Value

Description

7

O7

R

1*

reflects outgoing logic levels of pins defined as

outputs by Register 3

6O6

R

1*

5O5

R

1*

4O4

R

1*

3O3

R

1*

2O2

R

1*

1O1

R

1*

0O0

R

1*

Table 6.

Register 2 - Polarity Inversion register bit description

Legend: * default value.

Bit

Symbol

Access

Value

Description

7

N7

R/W

0*

inverts polarity of Input Port register data

0 = Input Port register data retained (default value)

1 = Input Port register data inverted

6

N6

R/W

0*

5

N5

R/W

0*

4

N4

R/W

0*

3

N3

R/W

0*

2

N2

R/W

0*

1

N1

R/W

0*

0

N0

R/W

0*