PCA9539D datasheet(8/31 Pages) NXP

8 / 31 page

PCA9539_PCA9539R_5

Product data sheet

Rev. 05 — 28 July 2008

8 of 31

NXP Semiconductors

PCA9539; PCA9539R

16-bit I2C-bus and SMBus low power I/O port with interrupt and reset

6.2.5 Registers 6 and 7: Conﬁguration registers

This register conﬁgures the directions of the I/O pins. If a bit in this register is set (written

with ‘1’), the corresponding port pin is enabled as an input with high-impedance output

driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is

enabled as an output. At reset, the device's ports are inputs.

6.3 Power-on reset

When power is applied to VDD, an internal power-on reset holds the PCA9539; PCA9539R

in a reset condition until VDD has reached VPOR. At that point, the reset condition is

released and the PCA9539; PCA9539R registers and SMBus state machine will initialize

to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device.

For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the

operating voltage.

6.4 RESET input

A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). In

the PCA9539 the registers and SMBus/I2C-bus state machine will be held in their default

state until the RESET input is once again HIGH. This input typically requires a pull-up to

VDD. In the PCA9539R, only the device state machine is initialized. The internal

general-purpose registers remain unchanged. Using the PCA9539R hardware reset pin

will only reset the I2C-bus interface should it be stuck LOW to regain access to the

I2C-bus. This allows the I/O pins to retain their last conﬁgured state so that they can keep

any lines in their previously deﬁned state and not cause system errors while the I2C-bus is

being restored.

6.5 I/O port

When an I/O is conﬁgured as an input, FETs Q1 and Q2 are off, creating a

high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.

If the I/O is conﬁgured as an output, then either Q1 or Q2 is on, depending on the state of

the Output port register. Care should be exercised if an external voltage is applied to an

I/O conﬁgured as an output because of the low-impedance path that exists between the

pin and either VDD or VSS.

Table 11.

Conﬁguration port 0 register

Bit

Symbol

C0.7

C0.6

C0.5

C0.4

C0.3

C0.2

C0.1

C0.0

Default

11111111

Table 12.

Conﬁguration port 1 register

Bit

Symbol

C1.7

C1.6

C1.5

C1.4

C1.3

C1.2

C1.1

C1.0

Default

11111111

PCA9539D Datasheet(PDF) 8 Page - NXP Semiconductors

PCA9539D Datasheet(HTML) 8 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Datasheet Download

Link URL