PCA9549 datasheet(13/25 Pages) NXP

13 / 25 page

PCA9549_2

Product data sheet

Rev. 02 — 13 July 2009

13 of 25

NXP Semiconductors

PCA9549

Octal bus switch with individually I2C-bus controlled enables

10. Dynamic characteristics

[1]

Pass gate propagation delay is calculated from the 6

Ω typical R

on and the 50 pF load capacitance.

[2]

After this period, the ﬁrst clock pulse is generated.

[3]

A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to

bridge the undeﬁned region of the falling edge of SCL.

[4]

Cb = total capacitance of one bus line in pF.

Table 8.

Dynamic characteristics

Symbol

Parameter

Conditions

Standard-mode

I2C-bus

Fast-mode I2C-bus

Unit

Min

Max

Min

Max

tPD

propagation delay

A to B;

VDD = 4.5 V to 5.5 V

0.25[1]

0.25[1] ns

fSCL

SCL clock frequency

100

400

kHz

tBUF

bus free time between a STOP and

START condition

4.7

1.3

µs

tHD;STA

hold time (repeated) START condition

[2]

4.0

0.6

µs

tLOW

LOW period of the SCL clock

4.7

1.3

µs

tHIGH

HIGH period of the SCL clock

4.0

0.6

µs

tSU;STA

set-up time for a repeated START

condition

4.7

0.6

µs

tSU;STO

set-up time for STOP condition

4.0

0.6

µs

tHD;DAT

data hold time

0[3]

3.45

0[3]

0.9

µs

tSU;DAT

data set-up time

250

100

rise time of both SDA and SCL

signals

1000

20 + 0.1Cb[4]

300

fall time of both SDA and SCL signals

300

20 + 0.1Cb[4]

300

capacitive load for each bus line

400

tSP

pulse width of spikes that must be

suppressed by the input ﬁlter

tVD;DAT

data valid time

HIGH-to-LOW

µs

LOW-to-HIGH

0.6

µs

tVD;ACK

data valid acknowledge time

µs

RESET

tw(rst)L

LOW-level reset time

trst

reset time

SDA clear

500

tREC;STA

recovery time to START condition

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