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PCA9632DP2 Datasheet(PDF) 14 Page - NXP Semiconductors |
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PCA9632DP2 Datasheet(HTML) 14 Page - NXP Semiconductors |
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14 / 38 page  PCA9632_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 15 July 2008 14 of 38 NXP Semiconductors PCA9632 4-bit Fm+ I2C-bus low power LED driver 7.3.5 Group frequency, GRPFREQ GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2 register) is equal to logic 1. Value in this register is a ‘don’t care’ when DMBLNK = 0. Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register). Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz) to FFh (10.73 seconds). (7) 7.3.6 LED driver output state, LEDOUT LDRx = 00 — LED driver x is off (default power-up state). LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking not controlled). LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx register. LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be controlled through its PWMx register and the GRPPWM registers. 7.3.7 I2C-bus subaddress 1 to 3, SUBADRx Subaddresses are programmable through the I2C-bus. Default power-up values are E2h, E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up (the corresponding SUBx bit in MODE1 register is equal to logic 0). Table 10. GRPFREQ - Group frequency register (address 07h) bit description Legend: * default value. Address Register Bit Symbol Access Value Description 07h GRPFREQ 7:0 GFRQ[7:0] R/W 0000 0000* GRPFREQ register global blinking period GFRQ 7:0 [] 1 + 24 ---------------------------------------- in onds sec () = Table 11. LEDOUT - LED driver output state register (address 08h) bit description Legend: * default value. Address Register Bit Symbol Access Value Description 08h LEDOUT 7:6 LDR3 R/W 00* LED3 output state control 5:4 LDR2 R/W 00* LED2 output state control 3:2 LDR1 R/W 00* LED1 output state control 1:0 LDR0 R/W 00* LED0 output state control Table 12. SUBADR1 to SUBADR3 - I2C-bus subaddress registers 0 to 3 (address 09h to 0Bh) bit description Legend: * default value. Address Register Bit Symbol Access Value Description 09h SUBADR1 7:1 A1[7:1] R/W 1110 001* I2C-bus subaddress 1 0 A1[0] R only 0* reserved 0Ah SUBADR2 7:1 A2[7:1] R/W 1110 010* I2C-bus subaddress 2 0 A2[0] R only 0* reserved 0Bh SUBADR3 7:1 A3[7:1] R/W 1110 100* I2C-bus subaddress 3 0 A3[0] R only 0* reserved |
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