APPLICATIONS INFORMATION

Theory of Operation

Input Configuration

500 W

500 W

Buffer

VCM

Buffer

1.6 pF

1.6pF

GND

S0293-01

AIN

AIN

AVDD5

AVDD5

ADS5463/5474/54RF63

GND

GND

~ 2.5 nH Bond Wire

~ 2.5 nH Bond Wire

~ 0.5pF

Package

~ 0.5pF

Package

~ 200fF

BondPad

~ 200fF

BondPad

ADS5474

The ADS5474 is a 14-bit, 400-MSPS, monolithic pipeline ADC. Its bipolar analog core operates from 5-V and

3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible outputs. The conversion

process is initiated by the rising edge of the external input clock. At that instant, the differential input signal is

captured by the input track-and-hold (T&H), and the input sample is converted sequentially by a series of lower

resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling

clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in

a data latency of 3.5 clock cycles, after which the output data are available as a 14-bit parallel word, coded in

offset binary format.

The analog input for the ADS5474 consists of an analog pseudo-differential buffer followed by a bipolar transistor

T&H. The analog buffer isolates the source driving the input of the ADC from any internal switching and presents

a high impedance that is easy to drive at high input frequencies, compared to an ADC without a buffered input.

The input common-mode is set internally through a 500-

Ω resistor connected from 3.1 V to each of the inputs

(common-mode is ~2.4V on 12- and 13-bit members of this family). This configuration results in a differential

input impedance of 1 k

Ω.

Figure 31. Analog Input Equivalent Circuit

For a full-scale differential input, each of the differential lines of the input signal (pins 16 and 17) swings

symmetrically between (3.1 V + 0.55 V) and (3.1 V – 0.55 V). This range means that each input has a maximum

with the characteristics of performance versus input amplitude demonstrated in Figure 18 and Figure 19. For

any external circuitry for this purpose.

18

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