1

7

1

1

1

1

1

1

S

Slave Address

Wr

A

A

Sr

Rd

A

8

1

1

1

1

ByteCountN

A

A

A

P

DataByte0

…

DataByteN-1

8

CommandCode

7

Slave Address

8

8

P

S

P

t(BUS)

tw(SCLL)

tw(SCLH)

tr

tf

th(START)

t

SU(SDA)

t

h(SDA)

tSU(STOP)

tSU(START)

tr

tf

SCL

SDA

VIH

VIL

VIH

VIL

A

Bit7(MSB)

Bit6

Bit0(LSB)

R

P

Master

R

P

SDA

SCL

C

BUS

Slave

CDCE949

CDCEL949

C

BUS

CDCE949

CDCEL949

www.ti.com

SCAS844D – AUGUST 2007 – REVISED MARCH 2010

Block Read Programming Sequence

Figure 11. Block Read Protocol

Timing Diagram for the SDA/SCL Serial Control Interface

Figure 12. Timing Diagram for the SDA/SCL Serial Control Interface

SDA/SCL Hardware Interface

Figure 13 shows how the CDCE949/CDCEL949 clock synthesizer is connected to the SDA/SCL serial interface

bus. Multiple devices can be connected to the bus but the speed may need to be reduced (400 kHz is the

maximum) if many devices are connected.

connected devices. The recommended pull-up value is 4.7 k

Ω. It must meet the minimum sink current of 3 mA at

Figure 13. SDA/SCL Hardware Interface

Copyright © 2007–2010, Texas Instruments Incorporated

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