CDCE949

CDCEL949

SCAS844D – AUGUST 2007 – REVISED MARCH 2010

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Table 9. Generic Configuration Register (continued)

Acronym

DESCRIPTION

06h

7-Bit Byte Count (Defines the number of Bytes which will be sent from this device at the next Block Read

7:1

BCOUNT

50h

transfer; all bytes must be read out to correctly finish the read cycle.)

0

EEWRITE

0b

0 – no EEPROM write cycle

1 – start EEPROM write cycle (internal configuration register is saved to the EEPROM)

07h-0Fh

—

—

0h

Reserved – do not write others than 0

(9)

NOTE: The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are written into the EEPROM.

The EEWRITE cycle is initiated by the rising edge of the EEWRITE-Bit. A static level high does not trigger an EEPROM WRITE cycle.

The EEWRITE-Bit must be reset low after the programming is completed. The programming status can be monitored by readout EEPIP.

If EELOCK is set high, no EEPROM programming will be possible.

16

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