TCA6408_09 datasheet(10/31 Pages) TI

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Interrupt Output (INT)

Bus Transactions

Writes

SCL

Start Condition

Data 1 Valid

SDA

Write to Port

Data Out

From Port

R/W

ACK From Slave

Data 1

Data to Port

Command Byte

Slave Address

1/0

SCL

SDA

StartCondition

R/W

ACKFromSlave

DatatoRegister

CommandByte

Slave Address

Data

TCA6408

LOW-VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER

WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007

An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the

signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original

setting, data is read from the port that generated the interrupt or in a stop event. Resetting occurs in the read

mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. In a

stop event, INT is cleared after the rising edge of SDA. Interrupts that occur during the ACK or NACK clock

pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the

I/Os after resetting is detected and is transmitted as INT.

Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output

cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the

state of the pin does not match the contents of the input port register.

The INT output has an open-drain structure and requires a pullup resistor to VCCP or VCCI depending on the

application. If the INT signal is connected back to the processor that provides the SCL signal to the TCA6408,

then the INT pin has to be connected to VCCI. If not, the INT pin can be connected to VCCP.

Data is exchanged between the master and TCA6408 through write and read commands.

Data is transmitted to the TCA6408 by sending the device address and setting the least-significant bit to a logic

0 (see Figure 4 for device address). The command byte is sent after the address and determines which register

receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one

write transmission.

Figure 6. Write to Output Port Register

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Figure 7. Write to Configuration or Polarity Inversion Registers

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