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Reads

0

0

1

S

0

0

0

AD

A

A

Data from Register

Slave Address

Slave Address

R/W

ACK From

Slave

Command Byte

S

0

0

1

0

0

0

R/W

1 A

Data

A

Data

Data from Register

NA P

Last Byte

At this moment, master-transmitter

becomes master-receiver, and

slave-receiver becomes

slave-transmitter

ACK From

Slave

ACK From

Slave

ACK From

Master

NACK From

Master

First byte

AD

DR

SCL

SDA

INT

Start

Condition

R/W

Read From

Port

Data Into

Port

Stop

Condition

ACK From

Master

NACK From

Master

ACK From

Slave

Data From Port

Slave Address

Data From Port

1

9

8

7

6

5

4

3

2

0

0

1

S

0

0

0

AD

DR

0

A

Data 1

Data 4

A

NA P

Data 2

Data 3

Data 4

Data 5

t

ph

t

ps

t

ir

t

iv

TCA6408

WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007

The bus master first must send the TCA6408 address with the least-significant bit set to a logic 0 (see Figure 4

for device address). The command byte is sent after the address and determines which register is accessed.

After a restart, the device address is sent again but, this time, the least-significant bit is set to a logic 1. Data

from the register defined by the command byte then is sent by the TCA6408 (see Figure 8 and Figure 9).

Data is clocked into the register on the rising edge of the ACK clock pulse.

Figure 8. Read From Register

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A.

Transfer of data can be stopped at any time by a stop condition. When this occurs, data present at the latest

acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read

input port register).

B.

This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address

call and actual data transfer from P port (see Figure 8).

Figure 9. Read Input Port Register

11

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