CAT9554 datasheet(1/16 Pages) ONSEMI

Part #	CAT9554

Description	8-bit I짼C and SMBus I/O Port with Interrupt

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CAT9554, CAT9554A

1

Doc. No. MD-9002, Rev. F

Characteristics subject to change without notice

8-bit I²C and SMBus I/O Port with Interrupt

FEATURES

400kHz I²C bus compatible

(1)

2.3V to 5.5V operation

Low stand-by current

5V tolerant I/Os

8 I/O pins that default to inputs at power-up

High drive capability

Individual I/O configuration

Polarity inversion register

Active low interrupt output

Internal power-on reset

No glitch on power-up

Noise filter on SDA/SCL inputs

Cascadable up to 8 devices

Industrial temperature range

RoHS-compliant 16-lead SOIC and TSSOP, and

16-pad TQFN (4 x 4mm) packages

APPLICATIONS

White goods (dishwashers, washing machines)

Handheld devices (cell phones, PDAs, digital

cameras)

Data Communications (routers, hubs and

servers)

DESCRIPTION

The CAT9554 and CAT9554A are CMOS devices that

provide 8-bit parallel input/output port expansion for

I²C and SMBus compatible applications. These I/O

expanders provide a simple solution in applications

where additional I/Os are needed: sensors, power

switches, LEDs, pushbuttons, and fans.

The CAT9554/9554A consist of an input port register,

an output port register, a configuration register, a

polarity

inversion

register

and

an

I²C/SMBus-

compatible serial interface.

Any of the eight I/Os can be configured as an input or

output by writing to the configuration register. The

system master can invert the CAT9554/9554A input

data by writing to the active-high polarity inversion

register.

The CAT9554/9554A features an active low interrupt

output which indicates to the system master that an

input state has changed.

The device’s extended addressing capability allows up

to 8 devices to share the same bus. The CAT9554A is

identical to the CAT9554 except the fixed part of the

I²C slave address is different. This allows up to 16 of

devices (eight CAT9554 and eight CAT9554A) to be

connected on the same bus.

For Ordering Information details, see page 15.

BLOCK DIAGRAM

(1)

Notes:

(1)

All I/Os are set to inputs at RESET.

8-BIT

I/O0

VCC

INT

WRITE pulse

READ pulse

LP FILTER

POWER-ON

RESET

INPUT

FILTER

I2C/SMBUS

CONTROL

A0

A1

A2

SDA

SCL

VCC

VSS

INPUT/

OUTPUT

PORTS

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

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