M34E02-FDW6TP datasheet(18/34 Pages) STMICROELECTRONICS

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Initial delivery state

M34E02, M34E02-F

18/34

Doc ID 10367 Rev 10

Initial delivery state

The device is delivered with all bits in the memory array set to ‘1’ (each Byte contains FFh).

Use within a DDR1/DDR2 DRAM module

In the application, the M34E02/M34E02-F is soldered directly in the printed circuit module.

The three Chip Enable inputs (E0, E1, E2) must be connected to VSS or VCC directly (that is

without using a pull-up or pull-down resistor) through the DIMM socket (see Table 4). The

pull-up resistors needed for normal behavior of the I2C bus are connected on the I2C bus of

the mother-board (as shown in Figure 11).

The Write Control (WC) of the M34E02/M34E02-F can be left unconnected. However,

connecting it to VSS is recommended, to maintain full read and write access.

5.1

Programming the M34E02 and M34E02-F

The situations in which the M34E02 and M34E02-F are programmed can be considered

under two headings:

●

when the DDR2 DRAM is isolated (not inserted on the PCB motherboard)

●

when the DDR2 DRAM is inserted on the PCB motherboard

5.1.1

Isolated DRAM module

With specific programming equipment, it is possible to define the M34E02/M34E02-F

content, using Byte and Page Write instructions, and its write-protection using the SWP and

CWP instructions. To issue the SWP and CWP instructions, the DRAM module must be

inserted in a specific slot where the E0 signal can be driven to VHV during the whole

instruction. This programming step is mainly intended for use by DRAM module makers,

whose end application manufacturers will want to clear this write-protection with the CWP

on their own specific programming equipment, to modify the lower 128 Bytes, and finally to

set permanently the write-protection with the PSWP instruction.

Table 4.

DRAM DIMM connections

DIMM position

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

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