56F8346 datasheet(49/178 Pages) FREESCALE

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Data Map

56F8346 Technical Data, Rev. 15

Freescale Semiconductor

Preliminary

4.4 Data Map

Note: Data Flash is NOT available on the 56F8146 device.

4.5 Flash Memory Map

Figure 4-1 illustrates the Flash Memory (FM) map on the system bus.

The Flash Memory is divided into three functional blocks. The Program and boot memories reside on the

1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced

from the vector table, providing only 19 bits of address.

2. If the VBA is set to 0200 (or VBA = 0000 for Mode 1, EMI_MODE = 0), the first two locations of the vector table are the

chip reset addresses; therefore, these locations are not interrupt vectors.

Table 4-6 Data Memory Map1

1. All addresses are 16-bit Word addresses, not byte addresses.

Begin/End

Address

EX = 02

2. In the Operating Mode Register (OMR).

EX = 1

X:$FF FFFF

X:$FF FF00

EOnCE

256 locations allocated

EOnCE

256 locations allocated

X:$FF FEFF

X:$01 0000

External Memory

X:$00 FFFF

X:$00 F000

On-Chip Peripherals

4096 locations allocated

On-Chip Peripherals

4096 locations allocated

X:$00 EFFF

X:$00 2000

External Memory

X:$00 1FFF

X:$00 1000

On-Chip Data Flash

8KB

X:$00 0FFF

X:$00 0000

On-Chip Data RAM

8KB3

3. The Data RAM is organized as a 2K x 32-bit memory to allow single-cycle long-word operations.

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