THS7360 datasheet(11/43 Pages) TI

11 / 43 page

THS7360

www.ti.com

SLOS674 – JUNE 2010

ELECTRICAL CHARACTERISTICS: VS+ = +5 V (continued)

At TA = +25°C, RL = 150 Ω to GND, Filter mode, and dc-coupled input/output, unless otherwise noted.

THS7360

TEST

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

LEVEL(1)

DC PERFORMANCE

VIN = 0 V, SD channels

160

315

Biased output voltage

VIN = 0 V, SF channels

120

300

Input voltage range

DC input, limited by output range

–0.1/1

VIN = –0.1 V, SD channels

140

200

Sync-tip clamp charge current

VIN = –0.1 V, SF channels

280

400

Input impedance

800 || 2

Ω || pF

OUTPUT CHARACTERISTICS

RL = 150 Ω to +2.5 V

4.85

RL = 150 Ω to GND

4.4

4.75

High output voltage swing

RL = 75 Ω to +2.5V

4.7

RL = 75 Ω to GND

4.5

RL = 150 Ω to +2.5 V (VIN = –0.2 V)

0.06

RL = 150 Ω to GND (VIN = –0.2 V)

0.05

0.12

Low output voltage swing

RL = 75 Ω to +2.5 V (VIN = –0.2 V)

0.1

RL = 75 Ω to GND (VIN = –0.2 V)

0.05

Output current (sourcing)

RL = 10 Ω to +2.5 V

Output current (sinking)

RL = 10 Ω to +2.5 V

POWER SUPPLY

Operating voltage

2.6

5.5

VIN = 0 V, all channels on

19.7

25.5

31.2

VIN = 0 V, SD channels on, SF channels off

7.5

9.5

Total quiescent current, no load

VIN = 0 V, SD channels off, SF channels on

13.7

21.7

VIN = 0 V, all channels off, VDISABLE = 3 V

0.5

Power-supply rejection ratio

At dc

(PSRR)

LOGIC CHARACTERISTICS(5)

VIH

Disabled or Bypass engaged

2.1

1.9

VIL

Enabled or Bypass disengaged

1.2

IIH

Applied voltage = 3.3 V

IIL

Applied voltage = 0 V

Disable time

100

Enable time

100

Bypass/filter switch time

(5)

The logic input pins default to a logic '0' condition when left floating.

Table 2. TRUTH TABLE: VS+ = +5 V

(1)

FILTER 1

FILTER 2

BYPASS SF

DESCRIPTION

Selects the standard definition filter (9.2 MHz) for the SF channels

Selects the enhanced definition filter (17 MHz) for the SF channels

Selects the high-definition filter (35 MHz) for the SF channels

Selects the full/true high-definition filter (70 MHz) for the SF channels

Bypasses the filters for the SF channels

(1)

The logic input pins default to a logic '0' condition when left floating.

Submit Documentation Feedback

Product Folder Link(s): THS7360

THS7360 Datasheet(PDF) 11 Page - Texas Instruments

THS7360 Datasheet(HTML) 11 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Datasheet Download

Link URL