DAC7728 datasheet(39/54 Pages) TI

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DAC7728

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SBAS461A – JUNE 2009 – REVISED NOVEMBER 2009

POWER-ON RESET

The DAC7728 contains a power-on reset circuit that controls the output during power-on and power down. This

feature is useful in applications where the known state of the DAC output during power-on is important. The

Offset DAC Registers, DAC Data Registers, and DAC latches are loaded with the value defined by the RSTSEL

pin, as shown in Table 8. The Gain Registers and Zero Registers are loaded with default values. The Input Data

Table 8. Bipolar Output Reset Values for Dual Power-Supply Operation

VALUE OF DAC

VALUE OF OFFSET

DATA REGISTER

DAC REGISTER

RSTSEL PIN

USB/BTC PIN

INPUT FORMAT

AND DAC LATCH

FOR GAIN = 6(1)

VOUT

DGND

Straight Binary

000h

99Ah

–Full-Scale

IOVDD

DGND

Straight Binary

800h

99Ah

0 V

DGND

IOVDD

Twos Complement

800h

19Ah

–Full-Scale

IOVDD

Twos Complement

000h

19Ah

0 V

(1)

Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the error for symmetrical output. The default value may vary

no more than ±2 LSB from the nominal number listed in this table.

In single-supply operation, the Offset DAC is turned off and the output is unipolar. The power-on reset is defined

as shown in Table 9.

Table 9. Unipolar Output Reset Values for Single Power-Supply Operation

VALUE OF DAC DATA

RSTSEL PIN

USB/BTC PIN

INPUT FORMAT

LATCH

VOUT

DGND

Straight Binary

000h

0 V

IOVDD

DGND

Straight Binary

800h

Midscale

DGND

IOVDD

Twos Complement

800h

0 V

IOVDD

Twos Complement

000h

Midscale

HARDWARE RESET

When the RST pin is low, the device is in hardware reset. All the analog outputs (VOUT-0 to VOUT-7), the DAC

registers, and the DAC latches are set to the reset values defined by the RSTSEL pin as shown in Table 8 and

Table 9. In addition, the Gain and Zero registers are loaded with default values, communication is disabled, and

the signals on R/W, CS , [D0:D11], and [A0:A4] are ignored (note that [D0:D11] are in a high-impedance state).

The Input Data Register is reset to 000h, independent of the RSTSEL state. On the rising edge of RST, the

analog outputs (VOUT-0 to VOUT-7) maintain the reset value as defined by the RSTSEL pin until a new value is

programmed. After RST goes high, the parallel interface returns to normal operation. CS must be set to a logic

high whenever RST is used.

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