TMS320DM6467 datasheet(39/357 Pages) TI

39 / 357 page

TMS320DM6467

Digital Media System-on-Chip

www.ti.com

SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009

Table 3-9. Asynchronous External Memory Interface (EMIFA) Terminal Functions (continued)

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

NAME

NO.

PCI_AD15/

IPD

I/O/Z

HD15/EM_D15

DVDD33

PCI_AD14/

IPD

I/O/Z

HD14 /EM_D14

DVDD33

PCI_AD13/

IPD

I/O/Z

HD13/EM_D13

DVDD33

PCI_AD12/

IPD

I/O/Z

HD12/EM_D12

DVDD33

PCI_AD11/

IPD

I/O/Z

HD11/EM_D11

DVDD33

PCI_AD10/

IPD

I/O/Z

HD10/EM_D10

DVDD33

PCI_AD9/

IPD

I/O/Z

HD9/EM_D9

DVDD33

These pins are multiplexed between PCI, HPI, and EMIFA.

PCI_AD8/

IPD

I/O/Z

For EMIFA mode, these pins are the 16-bit bidirectional data bus (EM_D[15:0])

HD8/EM_D8

DVDD33

[I/O/Z].

PCI_AD7/

IPD

When EMIFA is configured for an 8-bit asynchronous memory, only EM_D[7:0]

I/O/Z

HD7/EM_D7

DVDD33

pins are used.

PCI_AD6/

IPD

I/O/Z

HD6/EM_D6

DVDD33

PCI_AD5/

IPD

I/O/Z

HD5/EM_D5

DVDD33

PCI_AD4/

IPD

I/O/Z

HD4/EM_D4

DVDD33

PCI_AD3/

IPD

I/O/Z

HD3/EM_D3

DVDD33

PCI_AD2/

IPD

I/O/Z

HD2/EM_D2

DVDD33

PCI_AD1/

IPD

I/O/Z

HD1/EM_D1

DVDD33

PCI_AD0/

IPD

I/O/Z

HD0/EM_D0

DVDD33

EMIFA FUNCTIONAL PINS: NAND

PCI_IRDY/

This pin is multiplexed between PCI, HPI, and EMIFA.

IPU

HRDY/

I/O/Z

In EMIFA mode, this pin is address bit 17 output EM_A[17] (O/Z).

DVDD33

EM_A[17]/(CLE)

When used for EMIFA (NAND), this pin is Command Latch Enable output (CLE).

PCI_TRDY/

This pin is multiplexed between PCI, HPI, and EMIFA.

IPU

HHWIL/

I/O/Z

For EMIFA, this pin is address bit 16 output EM_A[16] (O/Z).

DVDD33

EM_A[16]/(ALE)

When used for EMIFA (NAND), this pin is Address Latch Enable output (ALE).

PCI_INTA/

This pin is multiplexed between PCI and EMIFA.

IPU

EM_WAIT2/

C11

I/O/Z

In EMIFA mode, this pin is wait state extension input 2 EM_WAIT2 (I).

DVDD33

(RDY2/BSY2)

When used for EMIFA (NAND), this pin is the ready/busy 2 input (RDY2/BSY2).

IORDY/

This pin is multiplexed between ATA, GPIO, and EMIFA.

IPU

GP[21]/EM_WAIT3/

D11

I/O/Z

In EMIFA mode, this pin is wait state extension input 3 EM_WAIT3 (I).

DVDD33

(RDY3/BSY3)

When used for EMIFA (NAND), this pin is the ready/busy 3 input (RDY3/BSY3).

DIOW/

This pin is multiplexed between ATA, GPIO, and EMIFA.

IPU

GP[20]/EM_WAIT4/

A11

I/O/Z

In EMIFA mode, this pin is wait state extension input 4 EM_WAIT4 (I).

DVDD33

(RDY4/BSY4)

When used for EMIFA (NAND), this pin is the ready/busy 4 input (RDY4/BSY4).

DIOR/

This pin is multiplexed between ATA, GPIO, and EMIFA.

IPU

GP[19]/EM_WAIT5/

E10

I/O/Z

For EMIFA, this pin is wait state extension input 5 EM_WAIT5 (I).

DVDD33

(RDY5/BSY5)

When used for EMIFA (NAND), this pin is the ready/busy 5 input (RDY5/BSY5).

PCI_SERR/

IPU

This pin is multiplexed between PCI, HPI, and EMIFA.

HDS1/

I/O/Z

DVDD33

In EMIFA mode, this pin is the output enable output EM_OE (O/Z).

EM_OE

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