 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AM1707BZKB4 Datasheet(PDF) 96 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
AM1707BZKB4 Datasheet(HTML) 96 Page - Texas Instruments |
|
|
96 / 199 page  AM1707 SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010 www.ti.com 6.17.1 McASP Peripheral Registers Description(s) Registers for the McASP are summarized in Table 6-44. The registers are accessed through the peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can also be accessed through the DMA port, as listed in Table 6-45 Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 6-46. Note that the AFIFO Write FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control registers are accessed through the peripheral configuration port. Table 6-44. McASP Registers Accessed Through Peripheral Configuration Port McASP0 McASP1 McASP2 ACRONYM REGISTER DESCRIPTION BYTE BYTE BYTE ADDRESS ADDRESS ADDRESS 0x01D0 0000 0x01D0 4000 0x01D0 8000 REV Revision identification register 0x01D0 0010 0x01D0 4010 0x01D0 8010 PFUNC Pin function register 0x01D0 0014 0x01D0 4014 0x01D0 8014 PDIR Pin direction register 0x01D0 0018 0x01D0 4018 0x01D0 8018 PDOUT Pin data output register 0x01D0 001C 0x01D0 401C 0x01D0 801C PDIN Read returns: Pin data input register 0x01D0 001C 0x01D0 401C 0x01D0 801C PDSET Writes affect: Pin data set register (alternate write address: PDOUT) 0x01D0 0020 0x01D0 4020 0x01D0 8020 PDCLR Pin data clear register (alternate write address: PDOUT) 0x01D0 0044 0x01D0 4044 0x01D0 8044 GBLCTL Global control register 0x01D0 0048 0x01D0 4048 0x01D0 8048 AMUTE Audio mute control register 0x01D0 004C 0x01D0 404C 0x01D0 804C DLBCTL Digital loopback control register 0x01D0 0050 0x01D0 4050 0x01D0 8050 DITCTL DIT mode control register 0x01D0 0060 0x01D0 4060 0x01D0 8060 RGBLCTL Receiver global control register: Alias of GBLCTL, only receive bits are affected - allows receiver to be reset independently from transmitter 0x01D0 0064 0x01D0 4064 0x01D0 8064 RMASK Receive format unit bit mask register 0x01D0 0068 0x01D0 4068 0x01D0 8068 RFMT Receive bit stream format register 0x01D0 006C 0x01D0 406C 0x01D0 806C AFSRCTL Receive frame sync control register 0x01D0 0070 0x01D0 4070 0x01D0 8070 ACLKRCTL Receive clock control register 0x01D0 0074 0x01D0 4074 0x01D0 8074 AHCLKRCTL Receive high-frequency clock control register 0x01D0 0078 0x01D0 4078 0x01D0 8078 RTDM Receive TDM time slot 0-31 register 0x01D0 007C 0x01D0 407C 0x01D0 807C RINTCTL Receiver interrupt control register 0x01D0 0080 0x01D0 4080 0x01D0 8080 RSTAT Receiver status register 0x01D0 0084 0x01D0 4084 0x01D0 8084 RSLOT Current receive TDM time slot register 0x01D0 0088 0x01D0 4088 0x01D0 8088 RCLKCHK Receive clock check control register 0x01D0 008C 0x01D0 408C 0x01D0 808C REVTCTL Receiver DMA event control register 0x01D0 00A0 0x01D0 40A0 0x01D0 80A0 XGBLCTL Transmitter global control register. Alias of GBLCTL, only transmit bits are affected - allows transmitter to be reset independently from receiver 0x01D0 00A4 0x01D0 40A4 0x01D0 80A4 XMASK Transmit format unit bit mask register 0x01D0 00A8 0x01D0 40A8 0x01D0 80A8 XFMT Transmit bit stream format register 0x01D0 00AC 0x01D0 40AC 0x01D0 80AC AFSXCTL Transmit frame sync control register 0x01D0 00B0 0x01D0 40B0 0x01D0 80B0 ACLKXCTL Transmit clock control register 0x01D0 00B4 0x01D0 40B4 0x01D0 80B4 AHCLKXCTL Transmit high-frequency clock control register 0x01D0 00B8 0x01D0 40B8 0x01D0 80B8 XTDM Transmit TDM time slot 0-31 register 0x01D0 00BC 0x01D0 40BC 0x01D0 80BC XINTCTL Transmitter interrupt control register 0x01D0 00C0 0x01D0 40C0 0x01D0 80C0 XSTAT Transmitter status register 0x01D0 00C4 0x01D0 40C4 0x01D0 80C4 XSLOT Current transmit TDM time slot register 0x01D0 00C8 0x01D0 40C8 0x01D0 80C8 XCLKCHK Transmit clock check control register 0x01D0 00CC 0x01D0 40CC 0x01D0 80CC XEVTCTL Transmitter DMA event control register 0x01D0 0100 0x01D0 4100 0x01D0 8100 DITCSRA0 Left (even TDM time slot) channel status register (DIT mode) 0 96 Peripheral Information and Electrical Specifications Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
