PACDN009 datasheet(6/10 Pages) ONSEMI

6 / 10 page

PACDN009

Rev. 3 | Page 6 of 10 | www.onsemi.com

Application Information

Design Considerations

In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to

minimize parasitic series inductances on the Supply/Ground rails as well as the signal trace segment

between the signal input (typically a connector) and the ESD protection device. Refer to Figure 1, which

illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance

back to the power supply is represented by L

1 and L2. The voltage VCL on the line being protected is:

CL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD ) / dt+ L2 x d(IESD ) / dt

where I

ESD is the ESD current pulse, and VSUPPLY is the positive supply voltage.

An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4

contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30

Amps in 1ns. Here d(I

ESD)/dt

can be approximated by

ΔI

ESD/Δt,

or 30/(1x10

-9). So just 10nH of series

inductance (L

1 and L2 combined) will lead to a 300V increment in VCL!

Similarly for negative ESD pulses, parasitic series inductance from the V

N pin to the ground rail will lead to

drastically increased negative voltage on the line being protected.

Another consideration is the output impedance of the power supply for fast transient currents. Most power

supplies exhibit a much higher output impedance to fast transient current spikes. In the V

equation

above, the V

SUPPLY term, in reality, is given by (VDC + IESD x ROUT), where VDC and ROUT are the nominal supply

DC output voltage and effective output impedance of the power supply respectively. As an example, a

OUT of 1 ohm would result in a 10V increment in VCL for a peak IESD of 10A.

If the inductances and resistance described above are close to zero, the rail-clamp ESD protection diodes

will do a good job of protection. However, since this is not possible in practical situations, a bypass

capacitor must be used to absorb the very high frequency ESD energy. So for any brand of rail-clamp

ESD protection diodes, a bypass capacitor should be connected between the V

P pin of the diodes and the

ground plane (V

N pin of the diodes) as shown in the Application Circuit diagram below. A value of 0.22µF

is adequate for IEC-61000-4-2 level 4 contact discharge protection (+8kV). Ceramic chip capacitors

mounted with short printed circuit board traces are good choices for this application. Electrolytic

capacitors should be avoided as they have poor high frequency characteristics. For extra protection,

connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series

inductance inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher

than the maximum supply voltage.

As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of

expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as

close to the V

P pin of the Protection Array as possible, with minimum PCB trace lengths to the power

supply, ground planes and between the signal input and the ESD device to minimize stray series

inductance.

Additional Information

See also California Micro Devices Application Notes AP209, “Design Considerations for ESD Protection”

and AP219, "ESD Protection for USB 2.0 Systems"

PACDN009 Datasheet(PDF) 6 Page - ON Semiconductor

PACDN009 Datasheet(HTML) 6 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10

Datasheet Download

Link URL