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CDCE906PW Datasheet(PDF) 23 Page - Texas Instruments

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Part # CDCE906PW
Description  PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
PDF  42 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

CDCE906PW Datasheet(HTML) 23 Page - Texas Instruments

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5
10
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25
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35
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45
50
55
C=18pF
Upk =300mV
Frequency − MHz
21 W
ESR=60
ESR=50
ESR=40
ESR=30
ESR=25
ESR=15
XO
or
2LVCMOS
or
Differential
input
CLK_IN0
CLK_IN1
CLK_SEL (A)
Input Source Select
(From EEPROM)
CDCE906
SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007
In order to ensure a stable oscillating, a certain drive power must be applied. The CDCE906 features an input
oscillator with adaptive gain control which relieves the user to manually program the gain. The drive level is the
amount of power dissipated by the oscillating crystal unit and is usually specified in terms of power dissipated by
the resonator (equivalent series resistance (ESR)). Figure 16 gives the resulting drive level vs crystal frequency
and ESR.
Figure 16. Crystal Drive Power
For example, if a 27-MHz crystal with ESR of 50
Ω is used and 2
× C
L is 18 pF, the drive power is 21 µW. Drive
level should be held to a minimum to avoid over driving the crystal. The maximum power dissipation is specified
for each type of crystal in the oscillator specifications, i.e., 100
µW for the example above.
Single-Ended LVCMOS Clock Inputs
When selecting the LVCMOS clock mode, CLK_IN0 and CLK_IN1 act as regular clock inputs pins and can be
driven up to 167 MHz. Both clock inputs circuitry are equal in design and can be used independently to each
other (see Figure 17). The internal clock select bit, Byte 10, Bit [4], selects one of the two input clocks. CLK_IN0
is the default selection. There is also the option to program the external control pin S0/A0/CLK_SEL as clock
select pin, Byte 10, Bit [1:0].
The two clock inputs can be used for redundancy switching, i.e. to switch between a primary clock and
secondary clock. Note a phase difference between the clock inputs may require PLL correction. Also in case of
different frequencies between the primary and secondary clock, the PLL has to re-lock to the new frequency.
A.
CLK_SEL is optional and can be configured by EEPROM setting.
Figure 17. LVCMOS Clock Input Circuitry
Copyright © 2005–2007, Texas Instruments Incorporated
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Product Folder Link(s): CDCE906



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