AD5424 datasheet(19/32 Pages) AD

19 / 32 page

AD5424/AD5433/AD5445

Rev. B | Page 19 of 32

SINGLE-SUPPLY APPLICATIONS

Current Mode Operation

The current mode circuit in Figure 51 shows a typical circuit for

operation with a single 2.5 V to 5 V supply. IOUT2 and therefore

IOUT1 is biased positive by the amount applied to VBIAS. In this

configuration, the output voltage is given by

VOUT = [D × (RFB/RDAC) × (VBIAS – VIN)] + VBIAS

As D varies from 0 to 255 (AD5424), 0 to 1023 (AD5433),

or 0 to 4095 (AD5445), the output voltage varies from

VOUT = VBIAS to VOUT = 2VBIAS − VIN.

VBIAS should be a low impedance source capable of sinking and

sourcing all possible variations in current at the IOUT2 terminal.

ADDITIONAL PINS OMITTED FOR CLARITY

C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

NOTES:

VDD

VIN

VREF

GND

DAC

RFB

IOUT1

IOUT2

VBIAS

VOUT

Figure 51. Single-Supply Current Mode Operation

It is important to note that VIN is limited to low voltages because

the switches in the DAC ladder no longer have the same source-

drain drive voltage. As a result, their on resistance differs and

the linearity of the DAC degrades.

Voltage Switching Mode of Operation

Figure 52 shows these DACs operating in the voltage-switching

mode. The reference voltage, VIN, is applied to the IOUT1 pin,

IOUT2 is connected to AGND, and the output voltage is available

at the VREF terminal. In this configuration, a positive reference

voltage results in a positive output voltage, making single-

supply operation possible. The output from the DAC is voltage

at a constant impedance (the DAC ladder resistance), thus an

op amp is necessary to buffer the output voltage. The reference

input no longer sees a constant input impedance, but one that

varies with code. So, the voltage input should be driven from a

low impedance source.

VIN

VDD

VREF

VOUT

GND

DAC

RFB

IOUT1

IOUT2

ADDITIONAL PINS OMITTED FOR CLARITY

C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

NOTES:

Figure 52. Single-Supply Voltage-Switching Mode Operation

It is important to note that VIN is limited to low voltages because

the switches in the DAC ladder no longer have the same source-

drain drive voltage. As a result, their on resistance differs, which

degrades the linearity of the DAC. See Figure 18 to Figure 23.

Also, VIN must not go negative by more than 0.3 V,;otherwise,

an internal diode turns on, exceeding the maximum ratings of

the device. In this type of application, the full range of

multiplying capability of the DAC is lost.

POSITIVE OUTPUT VOLTAGE

Note that the output voltage polarity is opposite to the VREF

polarity for dc reference voltages. To achieve a positive voltage

output, an applied negative reference to the input of the DAC is

preferred over the output inversion through an inverting ampli-

fier because of the resistor tolerance errors. To generate a

negative reference, the reference can be level-shifted by an op

amp such that the VOUT and GND pins of the reference become

the virtual ground and –2.5 V respectively, as shown

in Figure 53.

VDD

RFB

IOUT1

IOUT2

VOUT = 0V TO +2.5V

GND

VDD = 5V

VREF

NOTES:

1ADDITIONAL PINS OMITTED FOR CLARITY.

2C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,

IF A1 IS A HIGH SPEED AMPLIFIER.

ADR03

VOUT

VIN

GND

–5V

+5V

–2.5V

Figure 53. Positive Voltage Output with Minimum of Components

AD5424 Datasheet(PDF) 19 Page - Analog Devices

AD5424 Datasheet(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL