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Preliminary
6-53
RF2642
Rev A2 010720
6
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
8
7
6
1
16
15
14
13
9
5
10
11
12
2
3
4
Logic
Control
C9
10 nF
Gain Select
C10
10 nF
VCC
C11
1nF
50
Ωµstrip
J5
LO IN
C12
1nF
T1
TRANS6
C7
1nF
C8
1nF
50
Ωµstrip
J4
IF IN
C1
1nF
L4
3.9 nH
R8*
DNI
50
Ωµstrip
J1
PA OUT
L1
8.2 nH
R1*
DNI
C2
10 nF
VPA2
L2
8.2 nH
R2*
DNI
C3
10 nF
VPA1
PD
C5
10 nF
C4
1nF
R3*
DNI
50
Ωµstrip
J2
PA IN
R4
820
Ω
R5
5.1
Ω
R6
820
Ω
FL1
FLT BP
C6
1nF
R7*
DNI
50
Ωµstrip
J3
MIX OUT
2642400B
NOTE:
1. R1, R2 and R8 are optional.
2. R4, R5 and R6 form T-attenuator with a loss of 1 dB.
For 0 dB loss, R4 and R6 are removed, and R5 is a 0
Ω short.
3. R3 and R7 are normally open.
4. FLT BP recommended is a Murata filter: SAFC836.5MC90T-TC12.
5. The microstrip on pin 4 is bridged to ground via 0
Ω 0402 size resistor.
The recommended setting is at maximum of PCB.
6. The microstrip on pin 3 is bridged to ground via 0
Ω resistor. The
recommended setting is at a distance of 35 mils from edge of device.
7. *DNI: Do Not Install
P1
1
2
3
CON3
P1-3
PD
GND
P2
1
2
3
CON3
P2-3
VCC
GND
P2-1
Gain Select
P3
1
2
3
CON3
P3-1
VPA1
GND
P3-3
VPA2
See Note 2
µstrip
µstrip
R9
0
Ω
R10
0
Ω
See Note 6
See Note 5
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