KC73125MP datasheet(4/18 Pages) SAMSUNG

4 / 18 page

1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA

KC73125MP

DC CHARACTERISTICS

CLOCK VOLTAGE CONDITIONS

Table 3. DC Characteristics

Item

Symbol

Min.

Typ.

Max.

Unit

Remark

Output stage drain bias

VDD

14.55

15.0

15.45

Output stage gate voltage

VGG

1.75

2.0

2.25

Output stage source voltage

VSS

Ground through 680

Ω

±5%

Substrate voltage adjustment range

VSUB

7.0

14.5

Fluctuation voltage range after substrate

voltage adjusted

∆V

SUB

-3

Reset gate voltage adjustment range

VRGL

0.0

2.0

Protection circuit bias voltage

VVL voltage of the vertical clock waveform

Output stage drain current

IDD

2.5

Table 4. Clock Voltage Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

Remark

Read-out clock voltage

VVT

14.55

15.0

15.45

High level

Vertical transfer clock voltage

VVH1 ~ VVH4

-0.05

0.0

0.05

VVH = (VVH1 + VVH2)/2

VVL1 ~ VVL4

-9.5

-9.0

-8.5

VVL = (VVL3 + VVL4)/2

Horizontal transfer clock voltage

VΦH

4.75

5.0

5.25

High

VHL

-0.05

0.0

0.05

Low

Charge reset clock voltage

VΦRG

4.75

5.0

5.25

High

VRGLH - VRGLL

0.8

Low

Substrate clock voltage

VΦSUB

20.0

23.0

25.0

Shutter

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