THS7364IPW datasheet(33/47 Pages) TI

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75 W

S-VideoY'1Out

CVBS1Out

CVBS

S-Video Y’

S-Video C’

Y'/G'

SD1OUT

SD2OUT

SD3OUT

DisableSD

GND

DisableFHD

FHD1OUT

FHD2OUT

FHD3OUT

Bypass FHD

SD1IN

SD2IN

SD3IN

S+

FHD1IN

FHD2IN

FHD3IN

BypassSD

THS7364

Bypass

SDLPF

Bypass

LPF

FHD

P' /B'

P' /R'

75 W

S-VideoC'1Out

75 W

Y'/G'1Out

75 W

P’ /B'1Out

75 W

P' /R'1Out

75 W

S-VideoY'1Out

CVBS1Out

75 W

S-VideoC'1Out

75 W

Y'/G'1Out

75 W

P' /B'1Out

75 W

P’ /R'1Out

75 W

+2.7Vto

+5V

Disable FHD

DisableSD

THS7364

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SBOS530 – AUGUST 2010

(1)

Figure 81. Typical Six-Channel System with DC-Coupled Line Driving and Two Outputs Per Channel

One concern of dc-coupling, however, arises if the

but power and thermal analysis should always be

line is terminated to ground. If the ac-bias input

examined in any system to ensure that no issues

configuration is used, the output of the THS7364 has

arise.

sure

use

RMS

power

and

not

a dc bias on the output, such as 1.6 V. With two lines

instantaneous power when evaluating the thermal

terminated to ground, this configuration allows a dc

performance.

current path to flow, such as 1.6 V/75-

Ω = 21.3 mA.

Note that the THS7364 can drive the line with

The result of this configuration is a slightly decreased

dc-coupling

regardless

the

input

mode

high output voltage swing and an increase in power

operation. The only requirement is to make sure the

dissipation of the THS7364. While the THS7364 was

video line has proper termination in series with the

designed to operate with a junction temperature of up

output (typically 75

Ω). This requirement helps isolate

to +125°C, care must be taken to ensure that the

capacitive loading effects from the THS7364 output.

junction temperature does not exceed this level or

Failure to isolate capacitive loads may result in

else long-term reliability could suffer. Using a 5-V

instabilities with the output buffer, potentially causing

supply, this configuration can result in an additional

ringing

oscillations

appear.

The

stray

dc power dissipation of (5 V – 1.6 V) × 21.3 mA =

capacitance appearing directly at the THS7364 output

72.5 mW per channel. With a 3.3-V supply, this

pins should be kept below 20 pF for the fixed SD filter

dissipation reduces to 36.2 mW per channel. The

channels and below 15 pF for the FHD filter

overall low quiescent current of the THS7364 design

channels. One way to help ensure this condition is

minimizes potential thermal issues even when using

satisfied is to make sure the 75-

Ω source resistor is

the TSSOP package at high ambient temperatures,

placed within 0.5 inches, or 12.7 mm, of the THS7364

output pin. If a large ac-coupling capacitor is used,

the capacitor should be placed after this resistor.

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