AD5755ACPZ datasheet(30/34 Pages) AD

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AD5755/AD5735

Preliminary Technical Data

Rev. PrG | Page 30 of 34

Table 38. Slew Rate Update Clock Options

SR_CLOCK

Update Clock Frequency (Hz)*

0000

64K

0001

32K

0010

16K

0011

0100

0101

0110

0111

500

1000

250

1001

125

1010

1011

1100

1101

1110

1111

0.5Hz

*Clock Frequencies accurate to ±TDB%.

Table 39. Slew_Rate Step Size Options

SR_STEP

AD5735 (12 BIT)

Step Size (LSBs)

AD5755 (16 BIT)

Step Size (LSBs)

000

1/16

001

1/8

010

1/4

011

100

101

110

128

111

256

The following equation describes the slew rate as a function of

the step size, the update clock frequency and the LSB size.

Size

LSB

Frequency

Clock

Update

Size

Step

Change

Output

Time

Slew

Where:

Slew Time is expressed in seconds

Output Change is expressed in Amps for IOUT or V olts for V OUT

W hen the slew rate control feature is enabled, all output

changes will change at the programmed slew rate, for example

if the CLEAR pin is asserted the output will slew to the clear

value at the programmed slew rate (assuming that Clear

channel is enabled to be cleared). T he update clock

frequency for any given value will be the same for all output

ranges, the step size however will vary across output ranges for

a given value of step size as the LSB size will be different for

each output range.

POWER DISSIPATION CONTROL

The AD5755/AD5735 contains integrated dynamic power

control using a DC-DC boost circuit allowing reductions in

power consumption from standard designs when using the part

in current output mode.

In standard current input module designs the load resistor

values can range from typically 50 ohm to 750 ohm. Output

module systems must source enough voltage to meet the

compliance voltage requirement across the full range of load

resistor values. For example, in a 4-20ma loop when driving

20ma a compliance voltage of >15V is required. When driving

20ma into a 50 ohm load only 1V compliance is required.

The AD5755/AD5735 circuitry senses the output voltage and

regulates this voltage to meet compliance requirements plus a

small headroom voltage.

DC-DC CONVERTERS

The AD5755/AD5735 contains 4 independent DCDC

converters. These are used to provide dynamic control of the

VBOOST supply voltage for each channel (See Figure 15). Figure

20 below shows the discreet components needed for the DCDC

circuitry and the following sections describe component

selection and operation of this circuitry.

Figure 20. DC-DC Circuit

DC-DC Operation

The on-board DC-DC converters use a constant frequency,

peak current mode control scheme to step-up an AVcc input in

the range 2.7 to 5.5v to drive the AD5755/AD5735 output

channel. These are designed to operate in discontinuous

conduction mode (DCM) with a duty cycle < 85%.

Discontinuous conduction mode refers to a mode of operation

where the inductor current goes to zero for an appreciable % of

the switching cycle. The DCDC converters are non

synchronous i.e. they require an external schottky diode.

DC-DC Output Voltage

When a channel current output is enabled the converter

regulates the Vboost supply to 7.5V or (Iout*Rload+2V),

whichever is greater. The maximum Vboost voltage is set in the

DC-DC Control Register (25, 27.3, 28.6 or 30V. See Table 32).

In voltage output mode, or in current output mode with the

output disabled, the converter regulates the VBOOST supply to

+15v (±8%).

AVcc

DCDC

SW_x

Vboost_x

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