SI4313 datasheet(21/52 Pages) SILABS

21 / 52 page

Si4313-B1

Rev. 0.5

3.2.3. RX State

The RX state may be entered from any of the Idle modes when the rxon bit is set to 1 in 'Register 07h. Operating

Mode and Function Control 1'. A built-in sequencer takes care of all the actions required to transition from one of

the IDLE modes to the RX state. The following sequence of events will occur automatically to get the chip into RX

mode when going from STANDBY mode to RX mode by setting the rxon bit:

1. Enable the main digital LDO and the Analog LDOs.

2. Start up crystal oscillator and wait until ready (controlled by internal timer).

3. Enable PLL.

4. Calibrate VCO (this action is skipped when the vcocal bit is "0", default value is "1").

5. Wait until PLL settles to required receive frequency (controlled by internal timer).

6. Enable receive circuits: LNA, mixers, and ADC.

7. Calibrate ADC (RC calibration).

8. Enable receive mode in the digital modem.

Depending on the configuration of the radio all or some of the following functions will be performed automatically by

the digital modem: AGC, AFC (optional), update status registers, bit synchronization, packet handling (optional)

including sync word, header check, and CRC.

3.2.4. Device Status

The operational status of the Si4313 can be read from the Device Status register, 'Register 02h'

3.3. Interrupts

The Si4313 is capable of generating an interrupt signal when certain events occur. The chip notifies the

microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal

will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown

below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers

03h-04h) containing the active Interrupt Status bit. The nIRQ output signal will then be reset until the next change in

status is detected. The interrupts must be enabled by the corresponding enable bit in the Interrupt Enable

Registers (Registers 05h-06h). All enabled interrupt bits will be cleared when the microcontroller reads the interrupt

status register. If the interrupt is not enabled when the event then it will not trigger the nIRQ pin, but the status may

still be read at anytime in the Interrupt Status registers.

Add

R/W

Func/Description

POR

Def

Device Status

ffovfl

ffunfl

rxffem

headerr freqerr

cps[1]

cps[2]

—

Add R/W Func/Description

POR

Def

Interrupt Status 1

ifferr

Reserved

irxffafull

iext

Reserved

ipkvalid

icrcerror

—

Interrupt Status 2

iswdet

ipreaval

ipreainval

irssi

iwut

ilbd

ichiprdy

ipor

—

R/W

Interrupt Enable 1

enfferr

Reserved

enrxffafull

enext

Reserved enpkvalid

encrcerror

00h

R/W

Interrupt Enable 1 enswdet enpreaval enpreainval

enrssi

enwut

enlbd

enchiprdy

enpor

01h

SI4313 Datasheet(PDF) 21 Page - Silicon Laboratories

SI4313 Datasheet(HTML) 21 Page - Silicon Laboratories

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL