SI4313 datasheet(32/52 Pages) SILABS

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Si4313-B1

Rev. 0.5

8. Auxiliary Functions

8.1. Smart Reset

The Si4313 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a

classic level threshold reset as well as a slope detector, POR. This reset circuit was designed to produce a reliable

reset signal under any circumstances. Reset will be initiated if any of the following conditions occurs:

 Initial power on, VDD starts from GND: reset is active till VDD reaches VRR (see table).

 When VDD decreases below VLD for any reason: reset is active till VDD reaches VRR.

 A software reset via Register 08h. "Operating Mode and Function Control 2," where reset is active for time

TSWRST.

 On the rising edge of a VDD glitch when the supply voltage exceeds the time functioned limit of Figure 10.

Figure 10. POR Glitch Parameters

The reset will initialize all registers to their default values. The reset signal is also available for output and use by

the microcontroller by using the default setting for GPIO_0. The inverted reset signal is available by default on

GPIO_1.

Table 13. POR Parameters

Parameter

Symbol

Comment

Min

Typ

Max

Unit

Release Reset Voltage

VRR

0.85

1.3

1.75

Power-On VDD Slope

SVDD

Tested VDD Slope Region

0.03

300

V/ms

Low VDD Limit

VLD

VLD<VRR

0.7

1.3

Software Reset Pulse

TSWRST

470

µs

Threshold Voltage

VTSD

0.4

Reference Slope

0.2

V/ms

VDD Glitch Reset Pulse

Also occurs after SDN, and initial

power on

516

Reset

t=0,

VDD starts to rise

VDD(t)

reset:

Vglitch>=0.4+t*0.2V/ms

actual VDD(t)

showing glitch

reset limit:

0.4V+t*0.2V/ms

VDD nom.

0.4V

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