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SI4313 Datasheet(PDF) 45 Page - Silicon Laboratories |
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SI4313 Datasheet(HTML) 45 Page - Silicon Laboratories |
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45 / 52 page ![]() Si4313-B1 Rev. 0.5 45 13. Pin Descriptions: Si4313 Pin Pin Name I/O Description 1 VDD_RF VDD +1.8 to +3.6 V supply voltage input to all analog +1.7 V regulators. The recommended VDD supply voltage is +3.3 V. 2 TX O Transmit output pin. The PA output is an open-drain connection; so, the L-C match must supply VDD (+3.3 VDC nominal) to this pin. 3NC — No Connect. 4RX — No Connect. 5 NC — No Connect. Not connected internally to any circuitry. 6 NC O No Connect 7 GPIO_0 I/O General Purpose Digital I/O that may be configured through the registers to perform various functions including: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, AntDiver- sity control, etc. See the SPI GPIO Configuration Registers, Address 0Bh, 0Ch, and 0Dh for more infor- mation. 8 GPIO_1 I/O 9 GPIO_2 I/O 10 VDR O Regulated Output Voltage of the Digital 1.7 V Regulator. A 1 µF decoupling capacitor is required. 11 NC — Internally this pin is tied to the paddle of the package. This pin should be left unconnected or connected to GND only. 12 VDD_DIG VDD +1.8 to +3.6 V supply voltage input to the Digital +1.7 V Regulator. The recommended VDD supply voltage is +3.3 V. 13 SDO O 0–VDD V digital output that provides a serial readback function of the internal control registers. 14 SDI I Serial Data input. 0–VDD V digital input. This pin provides the serial data stream for the 4-line serial data bus. 15 SCLK I Serial Clock input. 0–VDD V digital input. This pin provides the serial data clock function for the 4-line serial data bus. Data is clocked into the Si4313 on positive edge transitions. 16 nSEL I Serial Interface Select input. 0– VDD V digital input. This pin provides the Select/Enable function for the 4- line serial data bus. The signal is also used to signify burst read/write mode. 17 nIRQ O General Microcontroller Interrupt Status output. When the Si4313 exhibits anyone of the Interrupt Events the nIRQ pin will be set low=0. Please see the Control Logic registers section for more information on the Interrupt Events. The Microcontroller can then determine the state of the interrupt by reading a corre- sponding SPI Interrupt Status Registers, Address 03h and 04h. No external resistor pull-up is required, but it may be desirable if multiple interrupt lines are connected. 18 XOUT O Crystal Oscillator Output. Connect to an external 30 MHz crystal or leave floating if driving the Xin pin with an external signal source. 19 XIN I Crystal Oscillator Input. Connect to an external 30 MHz crystal or to an external source. If using an exter- nal clock source with no crystal, dc coupling with a nominal 0.8 VDC level is recommended with a mini- mum ac amplitude of 700 mVpp. 20 SDN I Shutdown input pin. 0–VDD V digital input. SDN should be = 0 in all modes except Shutdown mode. When SDN =1 the chip will be completely shutdown and the contents of the registers will be lost. PKG PADDLE_GND GND The exposed metal paddle on the bottom of the Si4313 supplies the RF and circuit ground(s) for the entire chip. It is very important that a good solder connection is made between this exposed metal paddle and the ground plane of the PCB underlying the Si4313. GND PAD 1 2 3 17 18 19 20 11 12 13 14 6 7 8 9 4 5 16 10 15 SCLK SDI SDO VDD_DIG NC VDD RX NC NC NC |
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