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AT25DF641A Datasheet(PDF) 14 Page - ATMEL Corporation

Part # AT25DF641A
Description  64-Mbit 2.7V Minimum Serial Peripheral Interface Serial Flash Memory
PDF  57 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT25DF641A Datasheet(HTML) 14 Page - ATMEL Corporation

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14
8693A–DFLASH–8/10
Atmel AT25DF641A [Preliminary]
While the device is programming, the Status Register can be read and will indicate that the
device is busy. For faster throughput, it is recommended that the Status Register be polled
rather than waiting the t
BP or tPP time to determine if the data bytes have finished programming.
At some point before the program cycle completes, the WEL bit in the Status Register will be
reset back to the logical “0” state.
The device also incorporates an intelligent programming algorithm that can detect when a byte
location fails to program properly. If a programming error arises, it will be indicated by the EPE
bit in the Status Register.
Figure 8-3.
Dual-Input Byte Program
Figure 8-4.
Dual-Input Page Program
8.3
Block Erase
A block of 4-, 32-, or 64-Kbytes can be erased (all bits set to the logical “1” state) in a single
operation by using one of three different opcodes for the Block Erase command. An opcode of
20h is used for a 4-Kbyte erase, an opcode of 52h is used for a 32-Kbyte erase, and an opcode
of D8h is used for a 64-Kbyte erase. Before a Block Erase command can be started, the Write
Enable command must have been previously issued to the device to set the WEL bit of the Sta-
tus Register to a logical “1” state.
To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h,
52h, or D8h) must be clocked into the device. After the opcode has been clocked in, the three
address bytes specifying an address within the 4-, 32-, or 64-Kbyte block to be erased must be
clocked in. Any additional data clocked into the device will be ignored. When the CS pin is deas-
serted, the device will erase the appropriate block. The erasing of the block is internally self-
timed and should take place in a time of t
BLKE.
SCK
CS
SI
SOI
MSB
MSB
23
1
0
10100010
67
5
410 11
9
812
33
35
34
31 32
29 30
OPCODE
AAAA
AAA
A A
ADDRESS BITS A23-A0
MSB
D7
D6
D5
D4
D3
D2
D1
D0
INPUT
DATA BYTE
HIGH-IMPEDANCE
SCK
CS
SI
SOI
MSB
MSB
23
1
0
10100010
67
5
410 11
9
812
39
37 38
33
36
35
34
31 32
29 30
OPCODE
AAAA
AAA
A A
MSB
MSB
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
ADDRESS BITS A23-A0
INPUT
DATA BYTE 1
MSB
D7
D6
D5
D4
D3
D2
D1
D0
INPUT
DATA BYTE n
INPUT
DATA BYTE 2
HIGH-IMPEDANCE



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