AT25DF641A datasheet(38/57 Pages) ATMEL

38 / 57 page

8693A–DFLASH–8/10

Atmel AT25DF641A [Preliminary]

Figure 11-1. Read Status Register

11.2

Write Status Register Byte 1

The Write Status Register Byte 1 command is used to modify the SPRL bit of the Status Regis-

ter and/or to perform a Global Protect or Global Unprotect operation. Before the Write Status

ously issued to set the WEL bit in the Status Register to a logical “1”.

To issue the Write Status Register Byte 1 command, the CS pin must first be asserted and the

opcode of 01h must be clocked into the device followed by one byte of data. The one byte of

data consists of the SPRL bit value, a don’t care bit, four data bits to denote whether a Global

Protect or Unprotect should be performed, and two additional don’t care bits (see Table 11-3).

Any additional data bytes that are sent to the device will be ignored. When the CS pin is deas-

serted, the SPRL bit in the Status Register will be modified, and the WEL bit in the Status

state of the SPRL bit before the Write Status Register Byte 1 command was executed (the prior

state of the SPRL bit) will determine whether or not a Global Protect or Global Unprotect will be

performed. Please refer to “Global Protect/Unprotect” on page 23 for more details.

The complete one byte of data must be clocked into the device before the CS pin is deasserted,

and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise,

the device will abort the operation, the state of the SPRL bit will not change, no potential Global

Protect or Unprotect will be performed, and the WEL bit in the Status Register will be reset back

to the logical “0” state.

If the WP pin is asserted, then the SPRL bit can only be set to a logical “1”. If an attempt is made

to reset the SPRL bit to a logical “0” while the WP pin is asserted, then the Write Status Register

Byte 1 command will be ignored, and the WEL bit in the Status Register will be reset back to the

logical “0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted.

SCK

MSB

00000101

410 11

812

21 22

15 16

13 14

23 24

28 29

OPCODE

MSB

DDDDDD

D D

MSB

DDDDD D

D D D

STATUS REGISTER

BYTE 1

STATUS REGISTER

BYTE 1

STATUS REGISTER

BYTE 2

HIGH-IMPEDANCE

Table 11-3.

Write Status Register Byte 1 Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SPRL

Global Protect/Unprotect

AT25DF641A Datasheet(PDF) 38 Page - ATMEL Corporation

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