AT25DF641A datasheet(34/57 Pages) ATMEL

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8693A–DFLASH–8/10

Atmel AT25DF641A [Preliminary]

At clock frequencies above f

CLK, the first two bytes of data output from the Status Register will

not be valid. Therefore, if operating at clock frequencies above f

CLK, at least four bytes of data

must be clocked out from the device in order to read the correct values of both bytes of the Sta-

tus Register.

Deasserting the CS pin will terminate the Read Status Register operation and put the SO pin

into a high-impedance state. The CS pin can be deasserted at any time and does not require

that a full byte of data be read.

Notes:

1. Only bit 7 of Status Register Byte 1 will be modified when using the Write Status Register Byte 1 command

2. R/W = Readable and writeable

R = Readable only

Table 11-1.

Status Register Format – Byte 1

Bit(1)

Name

Type(2)

Description

SPRL

Sector Protection Registers Locked

R/W

Sector Protection Registers are unlocked (default).

Sector Protection Registers are locked.

RES

Reserved for future use

Reserved for future use.

EPE

Erase/Program Error

Erase or program operation was successful.

Erase or program error detected.

WPP

Write Protect (WP) Pin Status

WP is asserted.

WP is deasserted.

3:2

SWP

Software Protection Status

All sectors are software unprotected (all Sector

Protection Registers are 0).

Some sectors are software protected. Read

individual Sector Protection Registers to determine

which sectors are protected.

Reserved for future use.

All sectors are software protected (all Sector

Protection Registers are 1 – default).

WEL

Write Enable Latch Status

Device is not write enabled (default).

Device is write enabled.

RDY/BSY

Ready/Busy Status

Device is ready.

Device is busy with an internal operation.

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