PT6530

V1.3

34

June 2010

6.15.3 OUTPUT PIN STATES DURING THE RESET PERIOD

Output Pin

State During Reset

S1/P1 to S8/P8

L (Note 2)

S9 to S73

L

COM1 to COM3

L

COM4/S74

L (Note 3)

KS1/S75. KS2/S76

L (Note 2)

KS3 to KS5

X (Note 4)

KS6

H

DO

H (Note 5)

Notes:

1. X = Don’t care

2. These output pins are forcibly set to the segment output function and held low.

3. When power is first applied, this output pin is forcibly set to the common output function and held low. However, when the DT control data bit is

transferred, either the common output or the segment output function is selected.

4. When power is first applied, these output pins are undefined until the S0 and S1 control data bits have been transferred.

5. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10KΩ is required. This pin remains high during the reset period

even if a key data read operation is performed.

6.16 NOTE ON TRANSFERRING DISPLAY DATA FROM THE

CONTROLLER

When using the PT6530 in 1/3 duty, applications transfer the display data (D1 to D228) in three operations, and in 1/4

duty, they transfer the display data (D1 to D300) in four operations. In either case, applications should transfer all of the

display data within 30ms to maintain the quality of the displayed image.