PT6552

V1.3

12

July 2010

NTERNAL BLOCK STATES DURING THE RESET PERIOD (WHEN

/RES IS LOW)

CLOCK GENERATOR

Reset is applied and the basic clock stops. However, the state of the OSC pin (the normal or sleep state) is determined

after the control data S0 and S1 has been sent.

COMMON DRIVER, SEGMENT DRIVER & LATCH

Reset is applied and the display is turned off. However, display data can be input to the LATCH.

KEY SCAN

Reset is applied and at the same time as the internal states are set to their initial states, the key scan operation is

disabled.

KEY BUFFER

Reset is applied and all the key data is set to the low level.

CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER

To allow serial data transfers, reset is not applied to these circuits.