LM4546B datasheet(18/27 Pages) NSC

18 / 27 page

AC Link Serial Interface Protocol

(Continued)

SDATA_OUT: Slots 5 to 12 – Reserved

These slots are not used by the LM4546B and should all be

stuffed with zeros by the AC ’97 Controller.

AC LINK INPUT FRAME:

SDATA_IN, CONTROLLER INPUT FROM LM4546B OUTPUT

The AC Link Input Frame contains status and PCM data from

the LM4546B control registers and stereo ADC. Input

Frames are carried on the SDATA_IN signal which is an

input to the AC ’97 Digital Audio Controller and an output

from the LM4546B codec. As shown in Figure 3, Input

Frames are constructed from thirteen time slots: one Tag

Slot followed by twelve Data Slots. The Tag Slot, Slot 0,

contains 16 bits of which 5 are used by the LM4546B. One is

used to indicate that the AC Link interface is fully operational

and the other 4 to indicate the validity of the data in the four

of the twelve following Data Slots that are used by the

LM4546B. Each Frame consists of 256 bits with each of the

twelve data slots containing 20 bits.

A new Input Frame is signaled with a low-to-high transition of

SYNC. SYNC should be clocked from the controller on a

rising edge of BIT_CLK and, as shown in Figure 6 and

Figure 7, the first tag bit in the Frame (“Codec Ready”) is

clocked from the LM4546B by the next rising edge of BIT-

_CLK. The LM4546B always clocks data to SDATA_IN on a

rising edge of BIT_CLK and the controller is expected to

sample SDATA_IN on the next falling edge. The LM4546B

samples SYNC on the falling edge of BIT_CLK.

Input and Output Frames are aligned to the same SYNC

transition.

The LM4546B checks each Frame to ensure 256 bits are

received. If a new Frame is detected (a low-to-high transition

on SYNC) before 256 bits are received from an old Frame

then the new Frame is ignored i.e. no valid data is sent on

SDATA_IN until a valid new Frame is detected.

The LM4546B transmits data MSB first, in a MSB justified

format. All reserved bits and slots are stuffed with "0"s by the

LM4546B.

SDATA_IN: Slot 0 – Codec/Slot Status Bits

The first bit (bit 15, “Codec Ready”) of slot 0 in the AC Link

Input Frame indicates when the codec’s AC Link digital

interface and its status/control registers are fully operational.

The digital controller is then able to read the LSBs from the

Powerdown Control/Stat register (26h) to determine the sta-

tus of the four main analog subsections. It is important to

check the status of these subsections after Initialization,

Cold Reset or the use of the powerdown modes in order to

minimize the risk of distorting analog signals passed before

the subsections are ready.

The 4 bits 14, 13, 12 and 11 indicate that the data in slots 1,

2, 3 and 4, respectively, are valid.

20123308

FIGURE 6. AC Link Input Frame

20123307

FIGURE 7. Start of AC Link Input Frame

LM4546B Datasheet(PDF) 18 Page - National Semiconductor (TI)

LM4546B Datasheet(HTML) 18 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Datasheet Download

Link URL