MAX6909 datasheet(13/33 Pages) MAXIM

13 / 33 page

After 1 month that translates to:

Total worst-case timekeeping error at the end of 1

month at +45°C is approximately 120s or 2min

(assumes negligible parasitic layout capacitance).

Figure 5 shows the register address definition. Table 3

is the hex register address/description.

Control Register (Write Protect Bit)

Bit 7 of the control register is the write protect bit. The

lower 7 bits (bits 0–6) are forced to zero and always read

a zero when read. Before any write operation to the clock

or RAM, bit 7 must be zero. When high, the write protect

bit prevents a write operation to any other register.

Hours Register (AM-PM/12-24 Mode)

Bit 7 of the hours register is defined as the 12-hour or

24-hour mode select bit. When high, the 12-hour mode

is selected. In the 12-hour mode, bit 5 is the AM/PM bit

with logic high being PM. In the 24-hour mode, bit 5 is

the second 10-hour bit (20h–23h).

Clock Burst

Addressing the clock burst register specifies burst

mode operation. In this mode, the first seven clock/cal-

endar registers and the control register can be consec-

utively read or written starting with bit 7 of address BEh

for a write and BFh for a read. If the write protect bit is

set high when a write clock/calendar burst mode is

specified, no data transfer occurs to any of the seven

clock/calendar registers or the control register. When

writing to the clock registers in the burst mode, all eight

registers must be written in order for the data to be

transferred. In addition, the WP bit in the control regis-

ter must be set to zero prior to a clock burst write.

RAM

The static RAM is 31 bytes addressed consecutively in

the RAM address space. Even address/commands

(C0h–FCh) are used for writes, and odd address/com-

mands (C1h–FDh) are used for reads. The contents of

the RAM are static and remain valid for VOUT down to

1.5V (typ).

RAM Burst

Addressing the RAM burst register specifies burst

mode operation. In this mode, the 31 RAM registers

can be consecutively read or written starting with bit 7

of address FEh for a write and FFh for a read. When

writing to RAM in burst mode, it is not necessary to

write all 31 bytes for the data to transfer. Each byte that

is written to is transferred to RAM regardless of whether

all 31 bytes are written.

Trickle Charge Register (MAX6910)

The trickle charge register controls the trickle charger

characteristics of the MAX6910. The trickle charger

functional schematic (Figure 6) shows the basic compo-

nents of the trickle charger. Table 4 details the bit set-

tings for trickle charger control. Trickle charge selection

(TCS) bits D7–D4 control the selection of the trickle

charger. In order to prevent accidental enabling, only a

pattern of 1010 enables the trickle charger. All other

patterns disable the trickle charger. The MAX6910 pow-

ers up with the trickle charger disabled. The diode

select (DS) bits (D3–D2) select whether two diodes or

no diodes are connected between VCC and BATT. If DS

is 10, no diode is selected; if DS is 01, two diodes are

selected. If DS is 00 or 11, the trickle charger is dis-

abled independent of the state of the TCS bits. The RS

bits (D1–D0) select the resistor that is connected

between VCC and BATT. If both RS bits are set to zero,

the trickle charger is disabled, regardless of any other

bit states in the trickle charger register. RS bits set to 10

select a 1.7K, 01 selects 2.9K, and 11 select 5K.

∆ =×











 ×











 ×











 ×

() =

day

()

min

0 000045

120 158

I2C-Compatible Real-Time Clocks with µP

Supervisor and NV RAM Controller

______________________________________________________________________________________

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

Frequency

32.768

kHz

Equivalent series resistance (ESR)

Ω

Parallel load capacitance

6pF

Q factor

40,000

Table 2. Acceptable Quartz Crystal Parameters

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