MAX6909 datasheet(21/33 Pages) MAXIM

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I2C-Compatible Real-Time Clocks with µP

Supervisor and NV RAM Controller

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Negative-Going VCC Transients

The MAX6909/MAX6910 are relatively immune to short-

duration negative transients (glitches) while issuing resets

to the µP during power-up, power-down, and brownout

conditions. Therefore, resetting the µP when VCC experi-

ences only small glitches is usually not recommended.

Maximum transient duration vs. reset comparator over-

drive (see the Typical Operating Characteristics) shows

the maximum pulse period that can occur on VCC for

which reset pulses are NOT generated. The graph was

produced using negative-going VCC pulses, starting at

3.6V and ending below the reset threshold by the mag-

nitude indicated (reset comparator overdrive). The

graph shows the typical maximum pulse width a nega-

tive-going VCC transient can have without causing a

reset. As the amplitude of the transient increases (i.e.,

goes farther below the reset threshold), the maximum

allowable pulse width decreases. Typically, a VCC tran-

sient that goes 60mV below the reset threshold and

lasts for 60µs or less does not cause a reset pulse to

be issued. A capacitor of at least 0.1µF mounted close

to the VCC pin provides additional transient immunity.

Interfacing to Microprocessors with

Bidirectional Reset Pins

Microprocessors with bidirectional reset pins, such as

the Motorola 68HC11 series, can contend with the

MAX6909/MAX6910 RESET or RESET outputs. If, for

example, the RESET output is driven high and the µP

wants to pull it low, indeterminate logic levels may

result. To correct this, connect a 4.7kΩ resistor

between the RESET output and the µP reset I/O as

shown in Figure 8. Buffer the RESET output to other

system components. The positive voltage supply for the

RESET pin is VCC. If VCC drops, then so does the VOH

of this pin.

Battery-On Output

The battery-on output, BATT ON, is an open-drain out-

put indicator of when the MAX6909/MAX6910 are pow-

ered from the backup battery input, BATT. When VCC

falls below the reset threshold, VRST, and below VBATT,

OUT switches from VCC to BATT and BATT ON is

asserted. When VCC rises above VBATT or the reset

threshold, VRST, OUT reconnects to VCC and BATT ON

is deasserted.

Watchdog Input

In the MAX6909/MAX6910, the watchdog circuit moni-

tors the µP’s activity. Data bit D4 in the configuration

period. The power-up default is 1.6s (D4 = 0). If D4 is

set to 1, then the watchdog timeout period is changed

to 200ms. Data bit D7 in the configuration register is the

watchdog enable function. A logic 0 disables the watch-

dog function and a logic 1 enables the watchdog func-

tion. The power-on reset state of WD EN is logic 0,

meaning the watchdog function is disabled. When D4 is

set to 1, the first watchdog timeout period following a

reset cycle is always 1.6s and reverts to 200ms after the

first WDI transition. This is to allow the µP to recover

after a RESET interrupt. If the µP does not toggle the

WDI within the register-selectable watchdog timeout

period, RESET and RESET are asserted for 200ms. At

the same time, bits D4 and D7 in the configuration regis-

ter are reset. These bits have to be rewritten to enable

the watchdog and short timeout function again. While

RESET and RESET are asserted, all control inputs to the

MAX6909/MAX6910 are disabled (MR, CE IN, WDI, and

the 2-wire interface). Figure 9 shows the watchdog tim-

ing relationship.

MAX6909/

MAX6910

VCC

GND

VCC

GND

RESET

BUFFERED RESET TO OTHER SYSTEM

4.7kΩ

Figure 8. Interfacing to Microprocessors with Bidirectional

Reset I/O

VCC

RESET

WDI

tWD

tWDI

tWDS

VRST

tRP

RESET

Figure 9. Watchdog Timing Relationship

MAX6909 Datasheet(PDF) 21 Page - Maxim Integrated Products

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