MC54/74HC244A

MOTOROLA

High–Speed CMOS Logic Data

DL129 — Rev 6

4

SWITCHING WAVEFORMS

Figure 1.

Figure 2.

VCC

GND

tf

tr

DATA INPUT

A OR B

OUTPUT

YA OR YB

10%

50%

90%

10%

50%

90%

tTLH

tPLH

tPHL

tTHL

ENABLE

A OR B

OUTPUT Y

OUTPUT Y

50%

50%

50%

90%

10%

tPZL

tPLZ

tPZH

tPHZ

VCC

GND

HIGH

IMPEDANCE

VOL

VOH

HIGH

IMPEDANCE

TEST CIRCUITS

* Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 3. Test Circuit

* Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 4. Test Circuit

CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.

CONNECT TO GND WHEN

TESTING tPHZ AND tPZH.

1 k

Ω

PIN DESCRIPTIONS

INPUTS

A1, A2, A3, A4, B1, B2, B3, B4

(Pins 2, 4, 6, 8, 11, 13, 15, 17)

Data input pins. Data on these pins appear in noninverted

form on the corresponding Y outputs, when the outputs are

enabled.

CONTROLS

Enable A, Enable B (Pins 1, 19)

Output enables (active–low). When a low level is applied

to these pins, the outputs are enabled and the devices func-

tion as noninverting buffers. When a high level is applied, the

outputs assume the high impedance state.

OUTPUTS

YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4

(Pins 18, 16, 14, 12, 9, 7, 5, 3)

Device outputs. Depending upon the state of the output–

enable pins, these outputs are either noninverting outputs or

high–impedance outputs.