MC54/74HC244A

High–Speed CMOS Logic Data

DL129 — Rev 6

3

MOTOROLA

Guaranteed Limit

Unit

v 125_C

v 85_C

– 55 to

25

_C

VCC

V

Test Conditions

Parameter

Symbol

VOL

Maximum Low–Level Output

Voltage

Vin = VIL

|Iout| v 20 µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin = VIL

|Iout| v 2.4 mA

|Iout| v 6.0 mA

|Iout| v 7.8 mA

3.0

4.5

6.0

0.26

0.26

0.26

0.33

0.33

0.33

0.4

0.4

0.4

Iin

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0

µA

IOZ

Maximum Three–State Leakage

Current

Output in High–Impedance State

Vin = VIL or VIH

Vout = VCC or GND

6.0

± 0.5

± 5.0

± 10

µA

ICC

Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

Iout = 0 µA

6.0

4.0

40

160

µA

NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

Sb l

P

V

Guaranteed Limit

Ui

Symbol

Parameter

VCC

V

– 55 to

25

_C

v85_C

v125_C

Unit

tPLH,

tPHL

Maximum Propagation Delay, A to YA or B to YB

(Figures 1 and 3)

2.0

3.0

4.5

6.0

96

50

18

15

115

60

23

20

135

70

27

23

ns

tPLZ,

tPHZ

Maximum Propagation Delay, Output Enable to YA or YB

(Figures 2 and 4)

2.0

3.0

4.5

6.0

110

60

22

19

140

70

28

24

165

80

33

28

ns

tPZL,

tPZH

Maximum Propagation Delay, Output Enable to YA or YB

(Figures 2 and 4)

2.0

3.0

4.5

6.0

110

60

22

19

140

70

28

24

165

80

33

28

ns

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

2.0

3.0

4.5

6.0

60

23

12

10

75

27

15

13

90

32

18

15

ns

Cin

Maximum Input Capacitance

—

10

10

10

pF

Cout

Maximum Three–State Output Capacitance (Output in

High–Impedance State)

—

15

15

15

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

C

PDi

i

i

C

i

(P

B ff )*

Typical @ 25

°C, VCC = 5.0 V

F

CPD

Power Dissipation Capacitance (Per Buffer)*

34

pF

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).