DS1553 datasheet(4/20 Pages) MAXIM

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DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM

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Table 1. Operating Modes

VCC

DQ0–DQ7

MODE

POWER

VIH

High-Z

Deselect

Standby

VIL

DIN

Write

Active

VIL

VIH

DOUT

Read

Active

VCC > VPF

VIL

VIH

High-Z

Read

Active

VSO < VCC <VPF

High-Z

Deselect

CMOS Standby

<VBAT

High-Z

Data Retention

Battery Current

DATA READ MODE

The DS1553 is in read mode whenever CE (chip enable) is low and WE (write enable) is high. The

device architecture allows ripple-through access to any valid address location. Valid data is available at

the data input/output (DQ) pins within tAA after the last address input is stable, provided that CE and OE

access times are satisfied. If CE or OE access times are not met, valid data is available at the latter of

chip-enable access (tCEA) or at output-enable access time (tOEA). The state of the DQ pins is controlled by

and OE . If the outputs are activated before tAA, the data lines are driven to an intermediate state until

tAA. If the address inputs are changed while CE and OE remain valid, output data remains valid for

output data hold time (tOH) but will then go indeterminate until the next address access.

DATA WRITE MODE

The DS1553 is in write mode whenever WE and CE are in their active state. The start of a write is

referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout

the cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent

read or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for tDH

afterward. In a typical application, the OE signal is high during a write cycle. However, OE can be active

provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE

transitioning low, the data bus can become active with read data defined by the address inputs. A low

transition on WE will then disable the outputs tWEZ after WE goes active.

DATA RETENTION MODE

The 5V device is fully accessible, and data can be written and read only when VCC is greater than VPF.

However, when VCC is below the power-fail point (VPF)—the point at which write protection occurs—the

internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch

point VSO (battery supply level), device power is switched from the VCC pin to the internal backup lithium

battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal

levels.

The 3.3V device is fully accessible and data can be written and read only when VCC is greater than VPF.

When VCC falls below VPF, access to the device is inhibited. If VPF is less than VSO, the device power is

switched from VCC to the internal backup lithium battery when VCC drops below VPF. If VPF is greater

than VSO, the device power is switched from VCC to the internal backup lithium battery when VCC drops

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